Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-05 Thread Michal Simek
2012/11/2 Josh Cartwright : > On Fri, Nov 02, 2012 at 04:12:21PM +0100, Lars-Peter Clausen wrote: >> On 11/02/2012 02:38 PM, Josh Cartwright wrote: >> > On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: >> >> On 10/31/2012 07:58 PM, Josh Cartwright wrote: > [...] >> >>> +static

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-05 Thread Michal Simek
2012/11/2 Josh Cartwright josh.cartwri...@ni.com: On Fri, Nov 02, 2012 at 04:12:21PM +0100, Lars-Peter Clausen wrote: On 11/02/2012 02:38 PM, Josh Cartwright wrote: On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: On 10/31/2012 07:58 PM, Josh Cartwright wrote: [...]

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Josh Cartwright
On Fri, Nov 02, 2012 at 04:12:21PM +0100, Lars-Peter Clausen wrote: > On 11/02/2012 02:38 PM, Josh Cartwright wrote: > > On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: > >> On 10/31/2012 07:58 PM, Josh Cartwright wrote: [...] > >>> +static void __init

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Lars-Peter Clausen
On 11/02/2012 02:38 PM, Josh Cartwright wrote: > Thanks for the review. > > On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: >> On 10/31/2012 07:58 PM, Josh Cartwright wrote: >>> [...] >>> +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)&3)>>4]) >>> +#define

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Josh Cartwright
Thanks for the review. On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: > On 10/31/2012 07:58 PM, Josh Cartwright wrote: > > [...] > > +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)&3)>>4]) > > +#define PERIPH_CLK_CTRL_DIV(x) (((x)&0x3F00)>>8) > > A few

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Lars-Peter Clausen
On 10/31/2012 07:58 PM, Josh Cartwright wrote: > [...] > +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)&3)>>4]) > +#define PERIPH_CLK_CTRL_DIV(x) (((x)&0x3F00)>>8) A few more spaces wouldn't hurt ;) > [...] > +static void __init zynq_periph_clk_setup(struct device_node

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Lars-Peter Clausen
On 10/31/2012 07:58 PM, Josh Cartwright wrote: [...] +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)3)4]) +#define PERIPH_CLK_CTRL_DIV(x) (((x)0x3F00)8) A few more spaces wouldn't hurt ;) [...] +static void __init zynq_periph_clk_setup(struct device_node *np) +{ +

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Josh Cartwright
Thanks for the review. On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: On 10/31/2012 07:58 PM, Josh Cartwright wrote: [...] +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)3)4]) +#define PERIPH_CLK_CTRL_DIV(x) (((x)0x3F00)8) A few more spaces

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Lars-Peter Clausen
On 11/02/2012 02:38 PM, Josh Cartwright wrote: Thanks for the review. On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: On 10/31/2012 07:58 PM, Josh Cartwright wrote: [...] +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)3)4]) +#define

Re: [PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-11-02 Thread Josh Cartwright
On Fri, Nov 02, 2012 at 04:12:21PM +0100, Lars-Peter Clausen wrote: On 11/02/2012 02:38 PM, Josh Cartwright wrote: On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote: On 10/31/2012 07:58 PM, Josh Cartwright wrote: [...] +static void __init zynq_periph_clk_setup(struct

[PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-10-31 Thread Josh Cartwright
Add support for COMMON_CLK, and provide simplified models for the necessary clocks on the zynq-7000. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. Signed-off-by: Josh Cartwright ---

[PATCH 5/8] ARM: zynq: add COMMON_CLK support

2012-10-31 Thread Josh Cartwright
Add support for COMMON_CLK, and provide simplified models for the necessary clocks on the zynq-7000. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. Signed-off-by: Josh Cartwright josh.cartwri...@ni.com ---