On Thu, May 26, 2016 at 09:16:21PM -0400, Rich Felker wrote:
> Would you prefer I continue to submit this driver with new versions of
> the patch series, or separate it out for further review on its own?
It would be clearer to submit it separately.
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On Thu, May 26, 2016 at 09:16:21PM -0400, Rich Felker wrote:
> Would you prefer I continue to submit this driver with new versions of
> the patch series, or separate it out for further review on its own?
It would be clearer to submit it separately.
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On Wed, May 25, 2016 at 11:17:08AM +0100, Mark Brown wrote:
> On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:
>
> > changes based on ml discussion of the v2 patch. The chipselect change
> > has not been made yet, except for rewriting the current logic to be
> > more clear. If the
On Wed, May 25, 2016 at 11:17:08AM +0100, Mark Brown wrote:
> On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:
>
> > changes based on ml discussion of the v2 patch. The chipselect change
> > has not been made yet, except for rewriting the current logic to be
> > more clear. If the
On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:
> changes based on ml discussion of the v2 patch. The chipselect change
> has not been made yet, except for rewriting the current logic to be
> more clear. If the decision is that it's needed, I can do it easily,
> but it needs testing
On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:
> changes based on ml discussion of the v2 patch. The chipselect change
> has not been made yet, except for rewriting the current logic to be
> more clear. If the decision is that it's needed, I can do it easily,
> but it needs testing
The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.
This driver will be extended to support
The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.
This driver will be extended to support
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