Hello,
Ocelot SoC belongs to a larger family of SoCs which use the same
interrupt controller with a few variation.
This series of patches add support for Luton, Serval and Jaguar2, they
are all MIPS based.
The first patches of the series also updates the binding documentation
with the new compatible strings.
Gregory
Changelog:
v3 -> v4
- Fix example in binding adding #address-cells property.
- Split the intial "irqchip: ocelot: Add support for Luton platforms"
patch with a new patch "irqchip: ocelot: prepare to support more
SoC"
- Move from u32 to u8 the type used inside the "struct chip_props"
- Keep the function ocelot_irq_unmask as is and use generic function
irq_gc_mask_disable_reg and irq_gc_unmask_enable_reg for Luton.
- Removed the irq_set_irqchip_state callback, actually this function
was never called on this platform and seemed in the end useless.
- Add acked-by from Alexandre on the last 2 patches.
v2 -> v3
- Fix new-line-at-end-of-file error in the yaml file
v1 -> v2:
- Convert the binding to yaml
- Squashed the patches adding new binding in a single one
Gregory CLEMENT (6):
dt-bindings: interrupt-controller: convert icpu intr bindings to
json-schema
dt-bindings: interrupt-controller: Add binding for few Microsemi
interrupt controllers
irqchip: ocelot: prepare to support more SoC
irqchip: ocelot: Add support for Luton platforms
irqchip: ocelot: Add support for Serval platforms
irqchip: ocelot: Add support for Jaguar2 platforms
.../mscc,ocelot-icpu-intr.txt | 21 ---
.../mscc,ocelot-icpu-intr.yaml | 64 ++++++++
drivers/irqchip/irq-mscc-ocelot.c | 146 +++++++++++++++---
3 files changed, 187 insertions(+), 44 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
--
2.29.2
