[PATCH v4 04/10] clk: mediatek: add mt6797 clock IDs

2017-04-07 Thread Mars Cheng 
Signed-off-by: Mars Cheng 
---
 include/dt-bindings/clock/mt6797-clk.h |  281 
 1 file changed, 281 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt6797-clk.h

diff --git a/include/dt-bindings/clock/mt6797-clk.h 
b/include/dt-bindings/clock/mt6797-clk.h
new file mode 100644
index 000..e48aa47
--- /dev/null
+++ b/include/dt-bindings/clock/mt6797-clk.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6797_H
+#define _DT_BINDINGS_CLK_MT6797_H
+
+/* TOPCKGEN */
+#defineCLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE   1
+#defineCLK_TOP_MUX_ULPOSC_AXI_CK_MUX   2
+#defineCLK_TOP_MUX_AXI 3
+#defineCLK_TOP_MUX_MEM 4
+#defineCLK_TOP_MUX_DDRPHYCFG   5
+#defineCLK_TOP_MUX_MM  6
+#defineCLK_TOP_MUX_PWM 7
+#defineCLK_TOP_MUX_VDEC8
+#defineCLK_TOP_MUX_VENC9
+#defineCLK_TOP_MUX_MFG 10
+#defineCLK_TOP_MUX_CAMTG   11
+#defineCLK_TOP_MUX_UART12
+#defineCLK_TOP_MUX_SPI 13
+#defineCLK_TOP_MUX_ULPOSC_SPI_CK_MUX   14
+#defineCLK_TOP_MUX_USB20   15
+#defineCLK_TOP_MUX_MSDC50_0_HCLK   16
+#defineCLK_TOP_MUX_MSDC50_017
+#defineCLK_TOP_MUX_MSDC30_118
+#defineCLK_TOP_MUX_MSDC30_219
+#defineCLK_TOP_MUX_AUDIO   20
+#defineCLK_TOP_MUX_AUD_INTBUS  21
+#defineCLK_TOP_MUX_PMICSPI 22
+#defineCLK_TOP_MUX_SCP 23
+#defineCLK_TOP_MUX_ATB 24
+#defineCLK_TOP_MUX_MJC 25
+#defineCLK_TOP_MUX_DPI026
+#defineCLK_TOP_MUX_AUD_1   27
+#defineCLK_TOP_MUX_AUD_2   28
+#defineCLK_TOP_MUX_SSUSB_TOP_SYS   29
+#defineCLK_TOP_MUX_SPM 30
+#defineCLK_TOP_MUX_BSI_SPI 31
+#defineCLK_TOP_MUX_AUDIO_H 32
+#defineCLK_TOP_MUX_ANC_MD3233
+#defineCLK_TOP_MUX_MFG_52M 34
+#defineCLK_TOP_SYSPLL_CK   35
+#defineCLK_TOP_SYSPLL_D2   36
+#defineCLK_TOP_SYSPLL1_D2  37
+#defineCLK_TOP_SYSPLL1_D4  38
+#defineCLK_TOP_SYSPLL1_D8  39
+#defineCLK_TOP_SYSPLL1_D16 40
+#defineCLK_TOP_SYSPLL_D3   41
+#defineCLK_TOP_SYSPLL_D3_D342
+#defineCLK_TOP_SYSPLL2_D2  43
+#defineCLK_TOP_SYSPLL2_D4  44
+#defineCLK_TOP_SYSPLL2_D8  45
+#defineCLK_TOP_SYSPLL_D5   46
+#defineCLK_TOP_SYSPLL3_D2  47
+#defineCLK_TOP_SYSPLL3_D4  48
+#defineCLK_TOP_SYSPLL_D7   49
+#defineCLK_TOP_SYSPLL4_D2  50
+#defineCLK_TOP_SYSPLL4_D4  51
+#defineCLK_TOP_UNIVPLL_CK  52
+#defineCLK_TOP_UNIVPLL_D7  53
+#defineCLK_TOP_UNIVPLL_D26 54
+#defineCLK_TOP_SSUSB_PHY_48M_CK55
+#defineCLK_TOP_USB_PHY48M_CK   56
+#defineCLK_TOP_UNIVPLL_D2  57
+#defineCLK_TOP_UNIVPLL1_D2 58
+#defineCLK_TOP_UNIVPLL1_D4 59
+#defineCLK_TOP_UNIVPLL1_D8 60
+#defineCLK_TOP_UNIVPLL_D3  61
+#defineCLK_TOP_UNIVPLL2_D2 62
+#defineCLK_TOP_UNIVPLL2_D4 63
+#defineCLK_TOP_UNIVPLL2_D8 64
+#defineCLK_TOP_UNIVPLL_D5  65
+#defineCLK_TOP_UNIVPLL3_D2 66
+#define

[PATCH v4 04/10] clk: mediatek: add mt6797 clock IDs

2017-04-07 Thread Mars Cheng 
Signed-off-by: Mars Cheng 
---
 include/dt-bindings/clock/mt6797-clk.h |  281 
 1 file changed, 281 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt6797-clk.h

diff --git a/include/dt-bindings/clock/mt6797-clk.h 
b/include/dt-bindings/clock/mt6797-clk.h
new file mode 100644
index 000..e48aa47
--- /dev/null
+++ b/include/dt-bindings/clock/mt6797-clk.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6797_H
+#define _DT_BINDINGS_CLK_MT6797_H
+
+/* TOPCKGEN */
+#defineCLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE   1
+#defineCLK_TOP_MUX_ULPOSC_AXI_CK_MUX   2
+#defineCLK_TOP_MUX_AXI 3
+#defineCLK_TOP_MUX_MEM 4
+#defineCLK_TOP_MUX_DDRPHYCFG   5
+#defineCLK_TOP_MUX_MM  6
+#defineCLK_TOP_MUX_PWM 7
+#defineCLK_TOP_MUX_VDEC8
+#defineCLK_TOP_MUX_VENC9
+#defineCLK_TOP_MUX_MFG 10
+#defineCLK_TOP_MUX_CAMTG   11
+#defineCLK_TOP_MUX_UART12
+#defineCLK_TOP_MUX_SPI 13
+#defineCLK_TOP_MUX_ULPOSC_SPI_CK_MUX   14
+#defineCLK_TOP_MUX_USB20   15
+#defineCLK_TOP_MUX_MSDC50_0_HCLK   16
+#defineCLK_TOP_MUX_MSDC50_017
+#defineCLK_TOP_MUX_MSDC30_118
+#defineCLK_TOP_MUX_MSDC30_219
+#defineCLK_TOP_MUX_AUDIO   20
+#defineCLK_TOP_MUX_AUD_INTBUS  21
+#defineCLK_TOP_MUX_PMICSPI 22
+#defineCLK_TOP_MUX_SCP 23
+#defineCLK_TOP_MUX_ATB 24
+#defineCLK_TOP_MUX_MJC 25
+#defineCLK_TOP_MUX_DPI026
+#defineCLK_TOP_MUX_AUD_1   27
+#defineCLK_TOP_MUX_AUD_2   28
+#defineCLK_TOP_MUX_SSUSB_TOP_SYS   29
+#defineCLK_TOP_MUX_SPM 30
+#defineCLK_TOP_MUX_BSI_SPI 31
+#defineCLK_TOP_MUX_AUDIO_H 32
+#defineCLK_TOP_MUX_ANC_MD3233
+#defineCLK_TOP_MUX_MFG_52M 34
+#defineCLK_TOP_SYSPLL_CK   35
+#defineCLK_TOP_SYSPLL_D2   36
+#defineCLK_TOP_SYSPLL1_D2  37
+#defineCLK_TOP_SYSPLL1_D4  38
+#defineCLK_TOP_SYSPLL1_D8  39
+#defineCLK_TOP_SYSPLL1_D16 40
+#defineCLK_TOP_SYSPLL_D3   41
+#defineCLK_TOP_SYSPLL_D3_D342
+#defineCLK_TOP_SYSPLL2_D2  43
+#defineCLK_TOP_SYSPLL2_D4  44
+#defineCLK_TOP_SYSPLL2_D8  45
+#defineCLK_TOP_SYSPLL_D5   46
+#defineCLK_TOP_SYSPLL3_D2  47
+#defineCLK_TOP_SYSPLL3_D4  48
+#defineCLK_TOP_SYSPLL_D7   49
+#defineCLK_TOP_SYSPLL4_D2  50
+#defineCLK_TOP_SYSPLL4_D4  51
+#defineCLK_TOP_UNIVPLL_CK  52
+#defineCLK_TOP_UNIVPLL_D7  53
+#defineCLK_TOP_UNIVPLL_D26 54
+#defineCLK_TOP_SSUSB_PHY_48M_CK55
+#defineCLK_TOP_USB_PHY48M_CK   56
+#defineCLK_TOP_UNIVPLL_D2  57
+#defineCLK_TOP_UNIVPLL1_D2 58
+#defineCLK_TOP_UNIVPLL1_D4 59
+#defineCLK_TOP_UNIVPLL1_D8 60
+#defineCLK_TOP_UNIVPLL_D3  61
+#defineCLK_TOP_UNIVPLL2_D2 62
+#defineCLK_TOP_UNIVPLL2_D4 63
+#defineCLK_TOP_UNIVPLL2_D8 64
+#defineCLK_TOP_UNIVPLL_D5  65
+#defineCLK_TOP_UNIVPLL3_D2 66
+#defineCLK_TOP_UNIVPLL3_D4 67
+#define