Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-10 Thread Jonathan Cameron
On 10 April 2017 17:34:33 BST, Rick Altherr wrote: >I don't believe there are any bindings changes or a need to revert. >Stephen's suggested changes are small improvements that make the driver >suitable for non-DT platforms (not an issue anytime soon) and help with >a

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-10 Thread Jonathan Cameron
On 10 April 2017 17:34:33 BST, Rick Altherr wrote: >I don't believe there are any bindings changes or a need to revert. >Stephen's suggested changes are small improvements that make the driver >suitable for non-DT platforms (not an issue anytime soon) and help with >a >planned refactor of the

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-08 Thread Jonathan Cameron
On 05/04/17 22:50, Stephen Boyd wrote: > On 04/01, Jonathan Cameron wrote: >> On 28/03/17 22:52, Rick Altherr wrote: >>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold >>> interrupts are supported by the hardware but are not currently implemented. >>> >>> Signed-off-by:

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-08 Thread Jonathan Cameron
On 05/04/17 22:50, Stephen Boyd wrote: > On 04/01, Jonathan Cameron wrote: >> On 28/03/17 22:52, Rick Altherr wrote: >>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold >>> interrupts are supported by the hardware but are not currently implemented. >>> >>> Signed-off-by:

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-05 Thread Stephen Boyd
On 04/01, Jonathan Cameron wrote: > On 28/03/17 22:52, Rick Altherr wrote: > > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > > interrupts are supported by the hardware but are not currently implemented. > > > > Signed-off-by: Rick Altherr > Two

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-05 Thread Stephen Boyd
On 04/01, Jonathan Cameron wrote: > On 28/03/17 22:52, Rick Altherr wrote: > > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > > interrupts are supported by the hardware but are not currently implemented. > > > > Signed-off-by: Rick Altherr > Two really trivial things

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-01 Thread Jonathan Cameron
On 31/03/17 21:57, Xo Wang wrote: > On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote: >> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote: >>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold >>> interrupts are supported by the

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-01 Thread Jonathan Cameron
On 31/03/17 21:57, Xo Wang wrote: > On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote: >> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote: >>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold >>> interrupts are supported by the hardware but are not currently

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-01 Thread Jonathan Cameron
On 28/03/17 22:52, Rick Altherr wrote: > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > interrupts are supported by the hardware but are not currently implemented. > > Signed-off-by: Rick Altherr Two really trivial things inline. I'll fix them

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-04-01 Thread Jonathan Cameron
On 28/03/17 22:52, Rick Altherr wrote: > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > interrupts are supported by the hardware but are not currently implemented. > > Signed-off-by: Rick Altherr Two really trivial things inline. I'll fix them whilst applying rather

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-03-31 Thread Xo Wang
On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote: > On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote: >> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold >> interrupts are supported by the hardware but are not currently

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-03-31 Thread Xo Wang
On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote: > On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote: >> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold >> interrupts are supported by the hardware but are not currently implemented. >> >> Signed-off-by: Rick Altherr

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-03-28 Thread Joel Stanley
On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote: > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > interrupts are supported by the hardware but are not currently implemented. > > Signed-off-by: Rick Altherr Reviewed-by:

Re: [PATCH v5 2/2] iio: Aspeed ADC

2017-03-28 Thread Joel Stanley
On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote: > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > interrupts are supported by the hardware but are not currently implemented. > > Signed-off-by: Rick Altherr Reviewed-by: Joel Stanley > --- > > Changes in v5: > -

[PATCH v5 2/2] iio: Aspeed ADC

2017-03-28 Thread Rick Altherr
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold interrupts are supported by the hardware but are not currently implemented. Signed-off-by: Rick Altherr --- Changes in v5: - Return EINVAL for unimplemented read/write channel infos. - Return EPERM for

[PATCH v5 2/2] iio: Aspeed ADC

2017-03-28 Thread Rick Altherr
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold interrupts are supported by the hardware but are not currently implemented. Signed-off-by: Rick Altherr --- Changes in v5: - Return EINVAL for unimplemented read/write channel infos. - Return EPERM for write attempts to