On 10 April 2017 17:34:33 BST, Rick Altherr wrote:
>I don't believe there are any bindings changes or a need to revert.
>Stephen's suggested changes are small improvements that make the driver
>suitable for non-DT platforms (not an issue anytime soon) and help with
>a
On 10 April 2017 17:34:33 BST, Rick Altherr wrote:
>I don't believe there are any bindings changes or a need to revert.
>Stephen's suggested changes are small improvements that make the driver
>suitable for non-DT platforms (not an issue anytime soon) and help with
>a
>planned refactor of the
On 05/04/17 22:50, Stephen Boyd wrote:
> On 04/01, Jonathan Cameron wrote:
>> On 28/03/17 22:52, Rick Altherr wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the hardware but are not currently implemented.
>>>
>>> Signed-off-by:
On 05/04/17 22:50, Stephen Boyd wrote:
> On 04/01, Jonathan Cameron wrote:
>> On 28/03/17 22:52, Rick Altherr wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the hardware but are not currently implemented.
>>>
>>> Signed-off-by:
On 04/01, Jonathan Cameron wrote:
> On 28/03/17 22:52, Rick Altherr wrote:
> > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> > interrupts are supported by the hardware but are not currently implemented.
> >
> > Signed-off-by: Rick Altherr
> Two
On 04/01, Jonathan Cameron wrote:
> On 28/03/17 22:52, Rick Altherr wrote:
> > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> > interrupts are supported by the hardware but are not currently implemented.
> >
> > Signed-off-by: Rick Altherr
> Two really trivial things
On 31/03/17 21:57, Xo Wang wrote:
> On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote:
>> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the
On 31/03/17 21:57, Xo Wang wrote:
> On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote:
>> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the hardware but are not currently
On 28/03/17 22:52, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr
Two really trivial things inline. I'll fix them
On 28/03/17 22:52, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr
Two really trivial things inline. I'll fix them whilst applying rather
On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote:
> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote:
>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>> interrupts are supported by the hardware but are not currently
On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley wrote:
> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote:
>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>> interrupts are supported by the hardware but are not currently implemented.
>>
>> Signed-off-by: Rick Altherr
On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr
Reviewed-by:
On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr
Reviewed-by: Joel Stanley
> ---
>
> Changes in v5:
> -
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: Rick Altherr
---
Changes in v5:
- Return EINVAL for unimplemented read/write channel infos.
- Return EPERM for
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: Rick Altherr
---
Changes in v5:
- Return EINVAL for unimplemented read/write channel infos.
- Return EPERM for write attempts to
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