>Your patch seems to be still word wrapped.
I hope this is better with the next version I'm going to
send out in a few minutes. Sorry about that.
>The noflags variant should be probably data driven too.
I rewrote the entire code to use an offset/size configuration
instead of declaring structs
Your patch seems to be still word wrapped.
I hope this is better with the next version I'm going to
send out in a few minutes. Sorry about that.
The noflags variant should be probably data driven too.
I rewrote the entire code to use an offset/size configuration
instead of declaring structs
On Wednesday 21 November 2007 12:02:38 Metzger, Markus T wrote:
Your patch seems to be still word wrapped.
>
> It seems we're avoiding to declare a structured data type and instead
> prefer to describe the type indirectly.
> We gain the flexibility to work with different data layouts.
> We
Hi,
> >and it seems like this patch and perfmon2 are going to have to
> >live with
> >each other... since they both require the use of the DS save area...
>
> Hmmm, this might require some synchronization between those two.
>
> Do you know how (accesses to) MSR's are managed by the kernel?
>> - the internal buffer interpretation as well as the corresponding
>> operations are selected at run-time by hardware detection
>> - different processors use different branch record formats
>
>I still think it would be far better if you would switch this
>over to be table
>driven. e.g.
- the internal buffer interpretation as well as the corresponding
operations are selected at run-time by hardware detection
- different processors use different branch record formats
I still think it would be far better if you would switch this
over to be table
driven. e.g. define a
Hi,
and it seems like this patch and perfmon2 are going to have to
live with
each other... since they both require the use of the DS save area...
Hmmm, this might require some synchronization between those two.
Do you know how (accesses to) MSR's are managed by the kernel?
There is a
On Wednesday 21 November 2007 12:02:38 Metzger, Markus T wrote:
Your patch seems to be still word wrapped.
It seems we're avoiding to declare a structured data type and instead
prefer to describe the type indirectly.
We gain the flexibility to work with different data layouts.
We loose
> >and it seems like this patch and perfmon2 are going to have to
> >live with
> >each other... since they both require the use of the DS save area...
>
> Hmmm, this might require some synchronization between those two.
>
> Do you know how (accesses to) MSR's are managed by the kernel?
There
t;B; [EMAIL PROTECTED]
>Subject: Re: [patch][v2] x86, ptrace: support for branch trace
>store(BTS)
>
>On Tue, 20 Nov 2007, dean gaudet wrote:
>
>> On Tue, 20 Nov 2007, Metzger, Markus T wrote:
>>
>> > +__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x
> We might want to add support for Netburst in 64bit mode some day.
> For today, I simply exclude Netburst for x86_64.
If you switched to table driven then adding another format like
this would be likely very easy. It's just that with the "own code for
everything"
method it becomes difficult.
t;B; [EMAIL PROTECTED]
>Subject: Re: [patch][v2] x86, ptrace: support for branch trace
>store(BTS)
>
>On Tue, 20 Nov 2007, Metzger, Markus T wrote:
>
>> +__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
>> +{
>> +switch (c->x86) {
>> +case 0
On Tue, 20 Nov 2007, dean gaudet wrote:
> On Tue, 20 Nov 2007, Metzger, Markus T wrote:
>
> > +__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
> > +{
> > + switch (c->x86) {
> > + case 0x6:
> > + switch (c->x86_model) {
> > +#ifdef __i386__
> > + case 0xD:
> >
On Tue, 20 Nov 2007, Metzger, Markus T wrote:
> +__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
> +{
> + switch (c->x86) {
> + case 0x6:
> + switch (c->x86_model) {
> +#ifdef __i386__
> + case 0xD:
> + case 0xE: /* Pentium M */
> +
> - the internal buffer interpretation as well as the corresponding
> operations are selected at run-time by hardware detection
> - different processors use different branch record formats
I still think it would be far better if you would switch this over to be table
driven. e.g. define a
Changes to previous version:
- moved task arrives/departs notifications to __switch_to_xtra()
- added _TIF_BTS_TRACE and _TIF_BTS_TRACE_TS to _TIF_WORK_CTXSW_*
- split _TIF_WORK_CTXSW into ~_PREV and ~_NEXT for x86_64
- ptrace_bts_init_intel() function called from init_intel()
- removed
Changes to previous version:
- moved task arrives/departs notifications to __switch_to_xtra()
- added _TIF_BTS_TRACE and _TIF_BTS_TRACE_TS to _TIF_WORK_CTXSW_*
- split _TIF_WORK_CTXSW into ~_PREV and ~_NEXT for x86_64
- ptrace_bts_init_intel() function called from init_intel()
- removed
- the internal buffer interpretation as well as the corresponding
operations are selected at run-time by hardware detection
- different processors use different branch record formats
I still think it would be far better if you would switch this over to be table
driven. e.g. define a
We might want to add support for Netburst in 64bit mode some day.
For today, I simply exclude Netburst for x86_64.
If you switched to table driven then adding another format like
this would be likely very easy. It's just that with the own code for
everything
method it becomes difficult.
: [patch][v2] x86, ptrace: support for branch trace
store(BTS)
On Tue, 20 Nov 2007, dean gaudet wrote:
On Tue, 20 Nov 2007, Metzger, Markus T wrote:
+__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
+{
+ switch (c-x86) {
+ case 0x6:
+ switch (c-x86_model
and it seems like this patch and perfmon2 are going to have to
live with
each other... since they both require the use of the DS save area...
Hmmm, this might require some synchronization between those two.
Do you know how (accesses to) MSR's are managed by the kernel?
There is a
On Tue, 20 Nov 2007, dean gaudet wrote:
On Tue, 20 Nov 2007, Metzger, Markus T wrote:
+__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
+{
+ switch (c-x86) {
+ case 0x6:
+ switch (c-x86_model) {
+#ifdef __i386__
+ case 0xD:
+ case
On Tue, 20 Nov 2007, Metzger, Markus T wrote:
+__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
+{
+ switch (c-x86) {
+ case 0x6:
+ switch (c-x86_model) {
+#ifdef __i386__
+ case 0xD:
+ case 0xE: /* Pentium M */
+
: [patch][v2] x86, ptrace: support for branch trace
store(BTS)
On Tue, 20 Nov 2007, Metzger, Markus T wrote:
+__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
+{
+switch (c-x86) {
+case 0x6:
+switch (c-x86_model) {
+#ifdef __i386__
+case 0xD
24 matches
Mail list logo
