On Thursday, September 6, 2007 10:50 am Yinghai Lu wrote:
> On 9/6/07, Jesse Barnes <[EMAIL PROTECTED]> wrote:
> > The problem with doing that is it would mean reserving some address
> > space for mmconfig usage. If the BIOS doesn't completely describe
> > all the reserved regions via e820 or
On 9/6/07, Jesse Barnes <[EMAIL PROTECTED]> wrote:
> The problem with doing that is it would mean reserving some address
> space for mmconfig usage. If the BIOS doesn't completely describe all
> the reserved regions via e820 or similar (apparently a common problem)
> we may end up making mmconfig
On 9/6/07, H. Peter Anvin <[EMAIL PROTECTED]> wrote:
> Well, to a first order of approximations, *all* northbridges have some
> sort of hardware registers to set mmconfig. We were talking yesterday
> that it might just make more sense to have code for various northbridges
> to configure mmconfig
On Thursday, September 6, 2007 2:48 am H. Peter Anvin wrote:
> Arne Georg Gleditsch wrote:
> > "Yinghai Lu" <[EMAIL PROTECTED]> writes:
> >> mmconfig is set in NB ( in new CPU), Do we still need to set
> >> mmconfig in SB like mcp55?
> >
> > I wasn't aware that the family 10h-chips had MSRs for
On Wed, 5 Sep 2007 17:00:27 +0200
"Andreas Herrmann" <[EMAIL PROTECTED]> wrote:
> On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote:
> > Well, they don't add any functionality, do they?
>
> They allow CF8/CFC to access ECS in cases where mmcfg is not working.
>
just for the
Arne Georg Gleditsch wrote:
"Yinghai Lu" <[EMAIL PROTECTED]> writes:
mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig
in SB like mcp55?
I wasn't aware that the family 10h-chips had MSRs for setting the
mmconfig address space directly in the NB (core?). Please disregard
"Yinghai Lu" <[EMAIL PROTECTED]> writes:
> mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig
> in SB like mcp55?
I wasn't aware that the family 10h-chips had MSRs for setting the
mmconfig address space directly in the NB (core?). Please disregard
my previous comment...
--
Arne Georg Gleditsch wrote:
Yinghai Lu [EMAIL PROTECTED] writes:
mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig
in SB like mcp55?
I wasn't aware that the family 10h-chips had MSRs for setting the
mmconfig address space directly in the NB (core?). Please disregard
my
On Wed, 5 Sep 2007 17:00:27 +0200
Andreas Herrmann [EMAIL PROTECTED] wrote:
On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote:
Well, they don't add any functionality, do they?
They allow CF8/CFC to access ECS in cases where mmcfg is not working.
just for the record; I have
On 9/6/07, H. Peter Anvin [EMAIL PROTECTED] wrote:
Well, to a first order of approximations, *all* northbridges have some
sort of hardware registers to set mmconfig. We were talking yesterday
that it might just make more sense to have code for various northbridges
to configure mmconfig
On 9/6/07, Jesse Barnes [EMAIL PROTECTED] wrote:
The problem with doing that is it would mean reserving some address
space for mmconfig usage. If the BIOS doesn't completely describe all
the reserved regions via e820 or similar (apparently a common problem)
we may end up making mmconfig
On Thursday, September 6, 2007 10:50 am Yinghai Lu wrote:
On 9/6/07, Jesse Barnes [EMAIL PROTECTED] wrote:
The problem with doing that is it would mean reserving some address
space for mmconfig usage. If the BIOS doesn't completely describe
all the reserved regions via e820 or similar
On 9/5/07, Andreas Herrmann <[EMAIL PROTECTED]> wrote:
> On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote:
> > "H. Peter Anvin" <[EMAIL PROTECTED]> writes:
> > > You're missing the point. How will the PCI bus transactions be
> > > different when using MMCONFIG versus your
On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote:
> "H. Peter Anvin" <[EMAIL PROTECTED]> writes:
> > You're missing the point. How will the PCI bus transactions be
> > different when using MMCONFIG versus your extended CF8 version?
>
> Conceivably this is useful if the IO
On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote:
> Well, they don't add any functionality, do they?
They allow CF8/CFC to access ECS in cases where mmcfg is not working.
> As such, I would agree with Andi -- we only
> need one method which can (correctly) access the full
"H. Peter Anvin" <[EMAIL PROTECTED]> writes:
> You're missing the point. How will the PCI bus transactions be
> different when using MMCONFIG versus your extended CF8 version?
Conceivably this is useful if the IO hub does not support MMCONFIG
accesses. The AMD 8111 does not, as far as I can
On 05.09.07 11:12:00, H. Peter Anvin wrote:
> >PCI Devices will not be the same on the bus since PCI read/write
> >functions will have different behavior. Without the patches you will
> >get an error when accessing ECS with CF8. We need ECS access for
> >patches that setups local interrupt
Robert Richter wrote:
On 05.09.07 06:58:58, H. Peter Anvin wrote:
But at the moment there is no need for further discussion on this subject
because Andi refuses to add support for Barcelona CF8/CFC ECS access.
Well, they don't add any functionality, do they? As such, I would agree
with Andi
On 05.09.07 06:58:58, H. Peter Anvin wrote:
> >But at the moment there is no need for further discussion on this subject
> >because Andi refuses to add support for Barcelona CF8/CFC ECS access.
> >
>
> Well, they don't add any functionality, do they? As such, I would agree
> with Andi -- we
Andreas Herrmann wrote:
On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote:
On Mon, 3 Sep 2007 11:17:18 +0200
"Andreas Herrmann" <[EMAIL PROTECTED]> wrote:
\>
Do you see any other issues besides the naming of the bit?
I wonder if we should key this off a PCI ID of the chipset
Andreas Herrmann wrote:
On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote:
On Mon, 3 Sep 2007 11:17:18 +0200
Andreas Herrmann [EMAIL PROTECTED] wrote:
\
Do you see any other issues besides the naming of the bit?
I wonder if we should key this off a PCI ID of the chipset rather
On 05.09.07 06:58:58, H. Peter Anvin wrote:
But at the moment there is no need for further discussion on this subject
because Andi refuses to add support for Barcelona CF8/CFC ECS access.
Well, they don't add any functionality, do they? As such, I would agree
with Andi -- we only need
Robert Richter wrote:
On 05.09.07 06:58:58, H. Peter Anvin wrote:
But at the moment there is no need for further discussion on this subject
because Andi refuses to add support for Barcelona CF8/CFC ECS access.
Well, they don't add any functionality, do they? As such, I would agree
with Andi
On 05.09.07 11:12:00, H. Peter Anvin wrote:
PCI Devices will not be the same on the bus since PCI read/write
functions will have different behavior. Without the patches you will
get an error when accessing ECS with CF8. We need ECS access for
patches that setups local interrupt vectors. This
H. Peter Anvin [EMAIL PROTECTED] writes:
You're missing the point. How will the PCI bus transactions be
different when using MMCONFIG versus your extended CF8 version?
Conceivably this is useful if the IO hub does not support MMCONFIG
accesses. The AMD 8111 does not, as far as I can see. At
On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote:
Well, they don't add any functionality, do they?
They allow CF8/CFC to access ECS in cases where mmcfg is not working.
As such, I would agree with Andi -- we only
need one method which can (correctly) access the full
On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote:
H. Peter Anvin [EMAIL PROTECTED] writes:
You're missing the point. How will the PCI bus transactions be
different when using MMCONFIG versus your extended CF8 version?
Conceivably this is useful if the IO hub does not
On 9/5/07, Andreas Herrmann [EMAIL PROTECTED] wrote:
On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote:
H. Peter Anvin [EMAIL PROTECTED] writes:
You're missing the point. How will the PCI bus transactions be
different when using MMCONFIG versus your extended CF8
> for setting mmio to accessing pci conf space, need to set sth on MSR.
> So the BIOS need to make it right..., otherwise OS need to set that
> when booting every cpu...to workaround it to make MMCONFIG working.
Yes the BIOS has to get some things right. After all that's the BIOS job.
And the
On 9/3/07, Andi Kleen <[EMAIL PROTECTED]> wrote:
> On Monday 03 September 2007 13:27, Robert Richter wrote:
>
> > On 03.09.07 12:15:03, Andi Kleen wrote:
> > > > But it is needed for some devices for full functionality.
> > >
> > > Examples? I can only think of PCI express error reporting, which
>
On 9/3/07, Andi Kleen [EMAIL PROTECTED] wrote:
On Monday 03 September 2007 13:27, Robert Richter wrote:
On 03.09.07 12:15:03, Andi Kleen wrote:
But it is needed for some devices for full functionality.
Examples? I can only think of PCI express error reporting, which
few drivers
for setting mmio to accessing pci conf space, need to set sth on MSR.
So the BIOS need to make it right..., otherwise OS need to set that
when booting every cpu...to workaround it to make MMCONFIG working.
Yes the BIOS has to get some things right. After all that's the BIOS job.
And the BIOS
On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote:
> On Mon, 3 Sep 2007 11:17:18 +0200
> "Andreas Herrmann" <[EMAIL PROTECTED]> wrote:
> \>
> > Do you see any other issues besides the naming of the bit?
>
> I wonder if we should key this off a PCI ID of the chipset rather than
>
On Monday 03 September 2007 15:48, Robert Richter wrote:
> Andi,
>
> On 03.09.07 14:48:41, Andi Kleen wrote:
> > > As said above, I do not see CF8 access as a workaround. I expect my
> > > system to work in the same way also if MMCONFIG is not available.
> >
> > It should boot sure, but exotic
Andi,
On 03.09.07 14:48:41, Andi Kleen wrote:
> > As said above, I do not see CF8 access as a workaround. I expect my
> > system to work in the same way also if MMCONFIG is not available.
>
> It should boot sure, but exotic stuff not working is not a major issue
It is not only about booting the
> And unfortunately this is too often the case.
On Barcelona systems?
> See for instance Robert Hancock's patch http://lkml.org/lkml/2007/5/30/2
> to enable MMCONFIG access in certain cases where BIOS did not correctly
> set up MCFG. Why are people working on such stuff if it is not serious
>
On Monday 03 September 2007 13:27, Robert Richter wrote:
> On 03.09.07 12:15:03, Andi Kleen wrote:
> > > But it is needed for some devices for full functionality.
> >
> > Examples? I can only think of PCI express error reporting, which
> > few drivers implement anyways and isn't really a show
On Mon, 3 Sep 2007 11:17:18 +0200
"Andreas Herrmann" <[EMAIL PROTECTED]> wrote:
\>
> Do you see any other issues besides the naming of the bit?
I wonder if we should key this off a PCI ID of the chipset rather than
the cpu id... I mean, how sure are you that all via chipsets connected
to the
On Mon, Sep 03, 2007 at 12:15:03PM +0200, Andi Kleen wrote:
>
> > But it is needed for some devices for full functionality.
>
> Examples? I can only think of PCI express error reporting, which
> few drivers implement anyways and isn't really a show stopper
> if it doesn't work. Besides I would
Andi,
On 03.09.07 12:15:03, Andi Kleen wrote:
> > But it is needed for some devices for full functionality.
>
> Examples? I can only think of PCI express error reporting, which
> few drivers implement anyways and isn't really a show stopper
> if it doesn't work. Besides I would be surprised if
> But it is needed for some devices for full functionality.
Examples? I can only think of PCI express error reporting, which
few drivers implement anyways and isn't really a show stopper
if it doesn't work. Besides I would be surprised if it even works
on the cheap desktop boards which have MCFG
On Mon, Sep 03, 2007 at 01:31:57AM -0700, Arjan van de Ven wrote:
> On Mon, 03 Sep 2007 10:17:39 +0200
> "Robert Richter" <[EMAIL PROTECTED]> wrote:
>
> > This patch implements PCI extended configuration space access for
> > AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
> >
On Sat, Sep 01, 2007 at 12:11:52PM +0200, Andi Kleen wrote:
> On Thursday 30 August 2007 19:43:14 Robert Richter wrote:
> > This patch implements PCI extended configuration space access for
> > AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
> > addresses. An x86 capability bit has
On Sat, Sep 01, 2007 at 12:11:52PM +0200, Andi Kleen wrote:
On Thursday 30 August 2007 19:43:14 Robert Richter wrote:
This patch implements PCI extended configuration space access for
AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
addresses. An x86 capability bit has been
On Mon, Sep 03, 2007 at 01:31:57AM -0700, Arjan van de Ven wrote:
On Mon, 03 Sep 2007 10:17:39 +0200
Robert Richter [EMAIL PROTECTED] wrote:
This patch implements PCI extended configuration space access for
AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
addresses. An x86
But it is needed for some devices for full functionality.
Examples? I can only think of PCI express error reporting, which
few drivers implement anyways and isn't really a show stopper
if it doesn't work. Besides I would be surprised if it even works
on the cheap desktop boards which have MCFG
Andi,
On 03.09.07 12:15:03, Andi Kleen wrote:
But it is needed for some devices for full functionality.
Examples? I can only think of PCI express error reporting, which
few drivers implement anyways and isn't really a show stopper
if it doesn't work. Besides I would be surprised if it
On Mon, Sep 03, 2007 at 12:15:03PM +0200, Andi Kleen wrote:
But it is needed for some devices for full functionality.
Examples? I can only think of PCI express error reporting, which
few drivers implement anyways and isn't really a show stopper
if it doesn't work. Besides I would be
On Mon, 3 Sep 2007 11:17:18 +0200
Andreas Herrmann [EMAIL PROTECTED] wrote:
\
Do you see any other issues besides the naming of the bit?
I wonder if we should key this off a PCI ID of the chipset rather than
the cpu id... I mean, how sure are you that all via chipsets connected
to the barcelona
And unfortunately this is too often the case.
On Barcelona systems?
See for instance Robert Hancock's patch http://lkml.org/lkml/2007/5/30/2
to enable MMCONFIG access in certain cases where BIOS did not correctly
set up MCFG. Why are people working on such stuff if it is not serious
On Monday 03 September 2007 13:27, Robert Richter wrote:
On 03.09.07 12:15:03, Andi Kleen wrote:
But it is needed for some devices for full functionality.
Examples? I can only think of PCI express error reporting, which
few drivers implement anyways and isn't really a show stopper
if
Andi,
On 03.09.07 14:48:41, Andi Kleen wrote:
As said above, I do not see CF8 access as a workaround. I expect my
system to work in the same way also if MMCONFIG is not available.
It should boot sure, but exotic stuff not working is not a major issue
It is not only about booting the
On Monday 03 September 2007 15:48, Robert Richter wrote:
Andi,
On 03.09.07 14:48:41, Andi Kleen wrote:
As said above, I do not see CF8 access as a workaround. I expect my
system to work in the same way also if MMCONFIG is not available.
It should boot sure, but exotic stuff not
On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote:
On Mon, 3 Sep 2007 11:17:18 +0200
Andreas Herrmann [EMAIL PROTECTED] wrote:
\
Do you see any other issues besides the naming of the bit?
I wonder if we should key this off a PCI ID of the chipset rather than
the cpu id...
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