Re: [perf] perf_fuzzer causes unchecked MSR access error

2021-03-04 Thread Liang, Kan
On 3/3/2021 3:22 PM, Vince Weaver wrote: On Wed, 3 Mar 2021, Liang, Kan wrote: We never use bit 58. It should be a new issue. Actually, KVM uses it. They create a fake event called VLBR_EVENT, which uses bit 58. It's introduced from the commit 097e4311cda9 ("perf/x86: Add constraint to

Re: [perf] perf_fuzzer causes unchecked MSR access error

2021-03-03 Thread Vince Weaver
On Wed, 3 Mar 2021, Liang, Kan wrote: > We never use bit 58. It should be a new issue. > Is it repeatable? yes, it's repeatable. (which I'm glad to see because it looks suspiciously like a memory bit flip) Though since it's a WARN_ONCE I have to reboot each time I want to test. If I get a

Re: [perf] perf_fuzzer causes unchecked MSR access error

2021-03-03 Thread Liang, Kan
On 3/3/2021 2:28 PM, Stephane Eranian wrote: On Wed, Mar 3, 2021 at 10:16 AM Vince Weaver wrote: Hello on my Haswell machine the perf_fuzzer managed to trigger this message: [117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to write 0x0400) at rIP:

Re: [perf] perf_fuzzer causes unchecked MSR access error

2021-03-03 Thread Stephane Eranian
On Wed, Mar 3, 2021 at 10:16 AM Vince Weaver wrote: > > Hello > > on my Haswell machine the perf_fuzzer managed to trigger this message: > > [117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to write > 0x0400) at rIP: 0x8106e4f4 (native_write_msr+0x4/0x20) >

[perf] perf_fuzzer causes unchecked MSR access error

2021-03-03 Thread Vince Weaver
Hello on my Haswell machine the perf_fuzzer managed to trigger this message: [117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to write 0x0400) at rIP: 0x8106e4f4 (native_write_msr+0x4/0x20) [117248.089957] Call Trace: [117248.092685]