; +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Qualcomm CAMSS ISP
> +
> +maintainers:
If you wa
t is "special" while, in reality... it's.. not.
It's just the same HW, after all.
On 1/19/2021 11:15 PM, AngeloGioacchino Del Regno wrote:
On new SoCs (SDM845 onwards) the Operating State Manager (OSM) is
being programmed in the bootloader and write-protected by the
hypervisor,
This adds support for the BOE BF060Y8M-AJ0 5.99" AMOLED module
that can be found in some F(x)Tec Pro1 and Elephone U1 devices.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gp
Document the boe,bf060y8m-aj0 panel.
Signed-off-by: AngeloGioacchino Del Regno
---
.../display/panel/boe,bf060y8m-aj0.yaml | 67 +++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/boe,bf060y8m-aj0.yaml
diff --git
Il 14/01/21 18:58, Bjorn Andersson ha scritto:
On Thu 14 Jan 11:49 CST 2021, AngeloGioacchino Del Regno wrote:
Document the new noise rejection properties "qcom,noise-reject-sda"
and "qcom,noise-reject-scl".
I presume these are unit-less levels?
Yes, there is no uni
Il 14/01/21 18:52, Bjorn Andersson ha scritto:
On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
The TCSR's PHY_CLK_SCHEME register is not available on all SoC
models, but some may still use a differential reference clock.
In preparation for these SoCs, add
Convert the qcom,i2c-qup binding to YAML schema.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 -
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 87 +++
2 files changed, 87 insertions(+), 40 deletions(-)
delete mode
device properties,
"qcom,noise-reject-sda" and "qcom,noise-reject-scl", which will
be used to set the level of noise rejection sensitivity.
If the properties are not specified, noise rejection will not be
enabled.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/i2c/b
Pro1 (MSM8998).
Changes in v3, as per Bjorn's review:
- Moved bitfield.h to maintain sort order
- Removed useless variable initialization
- Removed linebreak
Changes in v2:
- Fixed ARM (32) build error (added bitfield.h inclusion)
AngeloGioacchino Del Regno (3):
dt-bindings: i2c: qcom,i2c-qup
Document the new noise rejection properties "qcom,noise-reject-sda"
and "qcom,noise-reject-scl".
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Docu
.
This patch brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index
Support for the SDM630/660 series of SoCs was added to the driver:
document the qcom,sdm660-qusb2-phy compatible here.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
The SDM660 SoC uses the same configuration as MSM8996, but the
clock scheme uses a differential reference clock and none of
the SoCs in this series (630, 636 and others) have got a usable
PHY_CLK_SCHEME register in the TCSR for clk scheme detection.
Signed-off-by: AngeloGioacchino Del Regno
device properties,
"qcom,noise-reject-sda" and "qcom,noise-reject-scl", which will
be used to set the level of noise rejection sensitivity.
If the properties are not specified, noise rejection will not be
enabled.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/i2c/b
Convert the qcom,i2c-qup binding to YAML schema.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 -
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 87 +++
2 files changed, 87 insertions(+), 40 deletions(-)
delete mode
Pro1 (MSM8998).
Changes in v2:
- Fixed ARM (32) build error (added bitfield.h inclusion)
AngeloGioacchino Del Regno (3):
dt-bindings: i2c: qcom,i2c-qup: Convert txt to YAML schema
i2c: qup: Introduce SCL/SDA noise rejection
dt-bindings: i2c: qcom,i2c-qup: Document noise rejection properties
Document the new noise rejection properties "qcom,noise-reject-sda"
and "qcom,noise-reject-scl".
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Docu
Il 17/01/21 00:44, Sakari Ailus ha scritto:
Hi AngeloGioacchino,
On Wed, Jan 13, 2021 at 07:29:34PM +0100, AngeloGioacchino Del Regno wrote:
Add YAML device tree binding for IMX300 CMOS image sensor, and
the relevant MAINTAINERS entries.
Signed-off-by: AngeloGioacchino Del Regno
Il 15/01/21 06:31, Bjorn Andersson ha scritto:
On Wed 13 Jan 13:42 CST 2021, AngeloGioacchino Del Regno wrote:
Short-Circuit Protection (SCP) and Over-Current Protection (OCP) are
very important for regulators like LAB and IBB, which are designed to
provide from very small to relatively big
Il 17/01/21 16:45, Rob Herring ha scritto:
On Fri, 15 Jan 2021 19:52:52 +0100, AngeloGioacchino Del Regno wrote:
Add new qcom,sdm660-venus DT binding schema.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/media/qcom,sdm660-venus.yaml | 164 ++
1 file
ll in the working range limits)
is producing a current draw of more than 200mA on LAB.
Test OK.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb-regulator.c | 518 +-
1 file changed, 515 insertions(+), 3 deletions(-)
diff --git a/drivers/regula
Short-Circuit Protection (SCP) and Over-Current Protection (OCP) are
now implemented in the driver: document the interrupts.
This also fixes wrong documentation about the SCP interrupt for LAB.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
.../regulator/qcom
when the regulators are disabled (random voltage spikes etc).
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
drivers/regulator/qcom-labibb-regulator.c | 94 +++
1 file changed, 94 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b/dr
statements
- Moved irq get and request in probe function
- Changed short conditionals to full ones
- Removed useless check for ocp_irq_requested
- Fixed issues with YAML documentation
AngeloGioacchino Del Regno (7):
regulator: qcom-labibb: Implement voltage selector ops
regulator: q
,
- IBB (neg): -7700mV to -1400mV with 100mV stepping.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
drivers/regulator/qcom-labibb-regulator.c | 24 +++
1 file changed, 24 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b
-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb-regulator.c | 92 +++
1 file changed, 92 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b/drivers/regulator/qcom-labibb-regulator.c
index 0fe0f6bce4cf..0643713d6aad 100644
--- a/drivers/regulator
.
Assuming that the original intention was to have the SC IRQ in
both LAB and IBB, as per the names appearing in documentation,
fix the SCP interrupt.
While at it, also add the OCP interrupt in order to be able to
enable the Over-Current Protection feature, if requested.
Signed-off-by: AngeloGioacchino Del Regno
Document properties to configure soft start and discharge resistor
for LAB and IBB respectively.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
.../bindings/regulator/qcom-labibb-regulator.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git
Il 22/01/21 10:59, Linus Walleij ha scritto:
On Mon, Jan 18, 2021 at 3:38 PM AngeloGioacchino Del Regno
wrote:
By the way, this is really LEVEL irq, not EDGE... To avoid any
misunderstanding, I think that the best way to show you what I
am seeing is to just copy-paste the relevant piece from
Il 22/01/21 10:46, Viresh Kumar ha scritto:
On 21-01-21, 20:52, AngeloGioacchino Del Regno wrote:
**
** NOTE: To "view the full picture", please look at the following
** patch series:
** https://patchwork.kernel.org/project/linux-arm-msm/list/?ser
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 139 ++
1 file changed, 139 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/awinic
to
advertise this to an external interrupt controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-aw9523.c | 1122 ++
3 files changed, 1140 insertions(+)
create
to
advertise this to an external interrupt controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-aw9523.c | 1122 ++
3 files changed, 1140 insertions(+)
create
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 139 ++
1 file changed, 139 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/awinic
Il 25/01/21 11:40, Hans Verkuil ha scritto:
On 18/01/2021 18:45, AngeloGioacchino Del Regno wrote:
Il 18/01/21 18:21, Stanimir Varbanov ha scritto:
Hi Angelo,
Thanks for the patch!
On 1/15/21 8:52 PM, AngeloGioacchino Del Regno wrote:
Add the SDM660 DT compatible and its resource structure
2.039337] msm_fbdev_init+0x80/0xe0
[2.039735] msm_drm_bind+0x4d8/0x6d0
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/drm_modes.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 33fb2f05ce66..dd
30)
- Sony Xperia 10 (SDM630)
- Sony Xperia XZ Premium (MSM8998)
- F(x)Tec Pro 1 (MSM8998)
AngeloGioacchino Del Regno (3):
soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened
MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver
dt-bindings: soc: qcom:
range of SoCs,
from the mid-range to the high end ones including, but not limited
to, MSM8953/8996/8998, SDM630/636/660/845.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Kconfig | 17 +
drivers/soc/qcom/Makefile |1 +
drivers/soc/qcom/cpr-common.c | 35
Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver.
Signed-off-by: AngeloGioacchino Del Regno
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3f50d126dfcc..5c458052dbf4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14684,6
Add the bindings for the CPR3 driver to the documentation.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++
1 file changed, 241 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
diff
Add the MSM8998 to the blacklist since the CPU scaling is handled
out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
Add the SDM630, SDM636 and SDM660 to the blacklist since the CPU
scaling is handled out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq
support CPU scaling on SDM630
and MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 1244 -
1 file changed, 1212 insertions(+), 32 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-c
From: Manivannan Sadhasivam
Convert Qualcomm cpufreq devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 ---
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 204
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.
Signed-off-by: AngeloGioacchino Del
In order to fine-tune the frequency scaling from various governors,
allow to set a maximum transition latency from OPPs, which may be
different depending on the SoC.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 7 +++
1 file changed, 7 insertions
zle pieces, and they're also (basically) fully
accessible, which means that the OS must do it in order to get in the
same state as the newer ones and to get the entire scaling hardware to
start rolling.
AngeloGioacchino Del Regno (5):
cpufreq: blacklist SDM630/636/660 in cpufreq-dt-platdev
cpu
From: Manivannan Sadhasivam
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along with Domain ID (0/1).
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
support CPU scaling on SDM630
and MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 1240 -
1 file changed, 1208 insertions(+), 32 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-c
Add the bindings for the CPR3 driver to the documentation.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++
1 file changed, 241 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
diff
), while
needing SAW initialization for other purposes, like AVS control.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpuidle/Kconfig.arm| 1 +
drivers/cpuidle/cpuidle-qcom-spm.c | 294 ++---
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Mak
(MSM8998)
AngeloGioacchino Del Regno (3):
soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened
MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver
dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
.../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++
M
In order to fine-tune the frequency scaling from various governors,
allow to set a maximum transition latency from OPPs, which may be
different depending on the SoC.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 7 +++
1 file changed, 7 insertions
ll in the working range limits)
is producing a current draw of more than 200mA on LAB.
Test OK.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb-regulator.c | 518 +-
1 file changed, 515 insertions(+), 3 deletions(-)
diff --git a/drivers/regula
.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/spm.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 0c8aa9240c41..843732d12c54 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc
ntrollers in the SoC (like the OSM).
Contrary from MSM8974 and the like, this new version of the SPM just
requires us to set the initial parameters for AVS and *nothing else*, as
its states will be totally managed internally.
AngeloGioacchino Del Regno (3):
cpuidle: qcom_spm: Detach state m
ps
Tested on the following smartphones:
- Sony Xperia XA2(SDM630)
- Sony Xperia XA2 Ultra (SDM630)
- Sony Xperia 10 (SDM630)
- Sony Xperia XZ Premium (MSM8998)
- F(x)Tec Pro 1 (MSM8998)
AngeloGioacchino Del Regno (3):
soc: qcom: cpr: Move common functions to new file
d
.
Assuming that the original intention was to have the SC IRQ in
both LAB and IBB, as per the names appearing in documentation,
fix the SCP interrupt.
While at it, also add the OCP interrupt in order to be able to
enable the Over-Current Protection feature, if requested.
Signed-off-by: AngeloGioacchino Del Regno
range of SoCs,
from the mid-range to the high end ones including, but not limited
to, MSM8953/8996/8998, SDM630/636/660/845.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Kconfig | 17 +
drivers/soc/qcom/Makefile |1 +
drivers/soc/qcom/cpr-common.c | 35
rder to get in the
same state as the newer ones and to get the entire scaling hardware to
start rolling.
AngeloGioacchino Del Regno (5):
cpufreq: blacklist SDM630/636/660 in cpufreq-dt-platdev
cpufreq: blacklist MSM8998 in cpufreq-dt-platdev
cpufreq: qcom-hw: Implement CPRh aware OSM program
Il 18/01/21 18:57, Mark Brown ha scritto:
On Mon, Jan 18, 2021 at 06:54:26PM +0100, AngeloGioacchino Del Regno wrote:
Il 18/01/21 13:04, Mark Brown ha scritto:
Please do not submit new versions of already applied patches, please
submit incremental updates to the existing code. Modifying
Il 18/01/21 18:21, Stanimir Varbanov ha scritto:
Hi Angelo,
Thanks for the patch!
On 1/15/21 8:52 PM, AngeloGioacchino Del Regno wrote:
Add the SDM660 DT compatible and its resource structure, also
including support for the Venus pmdomains, in order to support
the Venus block in SDM630
Il 18/01/21 18:21, Stanimir Varbanov ha scritto:
On 1/17/21 9:23 PM, AngeloGioacchino Del Regno wrote:
Il 17/01/21 16:45, Rob Herring ha scritto:
On Fri, 15 Jan 2021 19:52:52 +0100, AngeloGioacchino Del Regno wrote:
Add new qcom,sdm660-venus DT binding schema.
Signed-off
Il 18/01/21 13:04, Mark Brown ha scritto:
On Sun, Jan 17, 2021 at 11:08:24PM +0100, AngeloGioacchino Del Regno wrote:
Implement {get,set}_voltage_sel, list_voltage, map_voltage with
the useful regulator regmap helpers in order to be able to manage
the voltage of LAB (positive) and IBB (negative
Il 18/01/21 14:19, Linus Walleij ha scritto:
On Mon, Jan 11, 2021 at 7:29 PM AngeloGioacchino Del Regno
wrote:
The Awinic AW9523(B) is a multi-function I2C gpio expander in a
TQFN-24L package, featuring PWM (max 37mA per pin, or total max
power 3.2Watts) for LED driving capability.
It has
From: Manivannan Sadhasivam
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along with Domain ID (0/1).
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.
Signed-off-by: AngeloGioacchino Del
map *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
Thanks for following my suggestion!
Reviewed-by: AngeloGioacchino Del Regno
less check for ocp_irq_requested
- Fixed issues with YAML documentation
AngeloGioacchino Del Regno (7):
regulator: qcom-labibb: Switch voltage ops from linear_range to linear
regulator: qcom-labibb: Implement current limiting
regulator: qcom-labibb: Implement pull-down, softstart, active
disc
The LAB and IBB regulator have just one range and it is useless
to use linear_range ops, as these are used to express multiple
linear ranges.
Switch list_voltage and map_voltage callbacks to *_linear instead.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/power/avs/qcom,cpr.txt | 131 +-
.../bindings/soc/qcom/qcom,cpr.yaml | 167 ++
MAINTAINERS | 2 +-
3 files changed, 169 insertions(+), 131 deletions(-)
create m
In preparation for implementing a new driver that will be handling
CPRv3, CPRv4 and CPR-Hardened, format out common functions to a new
file.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/cpr-common.c | 382
Il 19/01/21 16:07, Vinod Koul ha scritto:
Patch 2 had two blank lines getting inserted, I have fixed that up while
applying.. so:
Applied all, thanks
Thank you!
Document properties to configure soft start and discharge resistor
for LAB and IBB respectively.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
.../bindings/regulator/qcom-labibb-regulator.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git
Add the MSM8998 to the blacklist since the CPU scaling is handled
out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver.
Signed-off-by: AngeloGioacchino Del Regno
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 66052be495fb..3d9f9037f1c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14766,6
Short-Circuit Protection (SCP) and Over-Current Protection (OCP) are
now implemented in the driver: document the interrupts.
This also fixes wrong documentation about the SCP interrupt for LAB.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
.../regulator/qcom
-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb-regulator.c | 92 +++
1 file changed, 92 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b/drivers/regulator/qcom-labibb-regulator.c
index 0fe0f6bce4cf..0643713d6aad 100644
--- a/drivers/regulator
when the regulators are disabled (random voltage spikes etc).
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
drivers/regulator/qcom-labibb-regulator.c | 94 +++
1 file changed, 94 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b/dr
Il 20/01/21 00:17, Rob Herring ha scritto:
On Fri, Jan 15, 2021 at 07:52:52PM +0100, AngeloGioacchino Del Regno wrote:
Add new qcom,sdm660-venus DT binding schema.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/media/qcom,sdm660-venus.yaml | 164 ++
1 file
Add the SAWv4.1 parameters for MSM8998's Gold and Silver clusters.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/spm.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 843732d12c54..2e6312663293 100644
rdingly.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 339790ba585d..f9350b0284
From: Manivannan Sadhasivam
Convert Qualcomm cpufreq devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 ---
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 204
Add the SDM630, SDM636 and SDM660 to the blacklist since the CPU
scaling is handled out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq
Il 20/01/21 08:47, Taniya Das ha scritto:
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.
Hello Tanya,
Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead
Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which are also used by older GPU generations
which do
Il 14/01/21 23:33, Jeffrey Hugo ha scritto:
On Thu, Jan 14, 2021 at 3:13 PM AngeloGioacchino Del Regno
wrote:
Il 14/01/21 23:12, Jeffrey Hugo ha scritto:
On Sat, Jan 9, 2021 at 6:47 AM AngeloGioacchino Del Regno
wrote:
This clock enables the GPLL0 output to the multimedia subsystem
clock
Il 14/01/21 23:37, Jeffrey Hugo ha scritto:
On Thu, Jan 14, 2021 at 3:13 PM AngeloGioacchino Del Regno
wrote:
The GPU IOMMU depends on this clock and the hypervisor will crash
the SoC if this clock gets disabled because the secure contexts
that have been set on this IOMMU by the bootloader
, even 670MHz..) on this SoC.
To allow setting rates on the GPU PLL0, also define VCO boundaries
and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider.
With this change, the Adreno GPU is now able to scale through all
the available frequencies.
Signed-off-by: AngeloGioacchino Del Regno
To achieve CPR-Hardened functionality this clock must be on: add it
in order to be able to get it managed by the CPR3 driver.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/gcc-msm8998.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/qcom
is enabled.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/gcc-msm8998.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index c8d4c0348952..afea60a3ef43 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b
Add new clock definition to gcc-msm8998 dt-bindings.
Signed-off-by: AngeloGioacchino Del Regno
---
include/dt-bindings/clock/qcom,gcc-msm8998.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h
b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index
series was tested on:
- Sony Xperia XZ Premium (MSM8998)
- F(x)Tec Pro1 (MSM8998)
AngeloGioacchino Del Regno (11):
dt-bindings: clocks: gcc-msm8998: Add GCC_MMSS_GPLL0_CLK definition
clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock
dt-bindings: clock: gcc-msm8998: Add HMSS_GPLL0_CLK_SRC
Add new clock definition to gcc-msm8998 dt-bindings
Signed-off-by: AngeloGioacchino Del Regno
---
include/dt-bindings/clock/qcom,gcc-msm8998.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h
b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index
This clock enables the GPLL0 output to the multimedia subsystem
clock controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/gcc-msm8998.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
to force retain mem, but *not* peripheral when enabling
this GDSC (and, of course, the inverse on disablement).
With this change, the GPU finally works flawlessly on my four
different MSM8998 devices from two different manufacturers.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/gcc-msm8998.c | 100 -
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index afea60a3ef43..050c91af888e 100644
--- a/drivers/clk/qcom/gcc
Il 14/01/21 23:10, AngeloGioacchino Del Regno ha scritto:
This patch series fixes some issues with the MSM8998 clocks and, in
particular, brings a very important fix to the GCC PLLs.
These fixes are enhancing this SoC's stability and also makes it
possible to eventually enable the Adreno GPU
-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/mmcc-msm8998.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
index dd68983fe22e..475e00a5fdf4 100644
--- a/drivers/clk/qcom/mmcc-msm8998.c
+++ b
will experience random crashes without this change.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/clk/qcom/mmcc-msm8998.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
index 475e00a5fdf4..f9510a248a36
1 - 100 of 350 matches
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