On Fri, Nov 10, 2017 at 2:09 PM, Dave Hansen
wrote:
> On 11/10/2017 02:03 PM, Andy Lutomirski wrote:
>>> +static inline u16 kern_asid(u16 asid)
>>> +{
>>> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>>> + /*
>>> +* If PCID is on, ASID-aware code
On Fri, Nov 10, 2017 at 2:09 PM, Dave Hansen
wrote:
> On 11/10/2017 02:03 PM, Andy Lutomirski wrote:
>>> +static inline u16 kern_asid(u16 asid)
>>> +{
>>> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>>> + /*
>>> +* If PCID is on, ASID-aware code paths put the ASID+1 into the
On 11/10/2017 02:03 PM, Andy Lutomirski wrote:
>> +static inline u16 kern_asid(u16 asid)
>> +{
>> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>> + /*
>> +* If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
>> +* bits. This serves two purposes. It
On 11/10/2017 02:03 PM, Andy Lutomirski wrote:
>> +static inline u16 kern_asid(u16 asid)
>> +{
>> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>> + /*
>> +* If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
>> +* bits. This serves two purposes. It
On Fri, Nov 10, 2017 at 11:31 AM, Dave Hansen
wrote:
>
> From: Dave Hansen
>
> There are effectively two ASID types:
> 1. The one stored in the mmu_context that goes from 0->5
> 2. The one programmed into the hardware that goes from 1->6
On Fri, Nov 10, 2017 at 11:31 AM, Dave Hansen
wrote:
>
> From: Dave Hansen
>
> There are effectively two ASID types:
> 1. The one stored in the mmu_context that goes from 0->5
> 2. The one programmed into the hardware that goes from 1->6
>
> This consolidates the locations where converting
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