Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Hi Christoph,

Às 7:14 PM de 3/8/2017, Christoph Hellwig escreveu:
> On Wed, Mar 08, 2017 at 03:32:03PM +, Joao Pinto wrote:
>> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)  \
>>  ((0x3 << 20) | (region << 9) |  \
>>  (0x1 << 8)
> 
> Can you turn this and any similar macro into inline functions?
> 

Use an inline functions instead of macro is fine by me. In the initial patch I
implemented as a macro since it only does simple bit shifts and nothing else and
seemed simpler as a macro.

Thanks,
Joao

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Hi Christoph,

Às 7:14 PM de 3/8/2017, Christoph Hellwig escreveu:
> On Wed, Mar 08, 2017 at 03:32:03PM +, Joao Pinto wrote:
>> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)  \
>>  ((0x3 << 20) | (region << 9) |  \
>>  (0x1 << 8)
> 
> Can you turn this and any similar macro into inline functions?
> 

Use an inline functions instead of macro is fine by me. In the initial patch I
implemented as a macro since it only does simple bit shifts and nothing else and
seemed simpler as a macro.

Thanks,
Joao

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Christoph Hellwig]

On Wed, Mar 08, 2017 at 03:32:03PM +, Joao Pinto wrote:
> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)   \
>   ((0x3 << 20) | (region << 9) |  \
>   (0x1 << 8)

Can you turn this and any similar macro into inline functions?

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Christoph Hellwig]

On Wed, Mar 08, 2017 at 03:32:03PM +, Joao Pinto wrote:
> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)   \
>   ((0x3 << 20) | (region << 9) |  \
>   (0x1 << 8)

Can you turn this and any similar macro into inline functions?

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I 
>> ---
>>  drivers/pci/dwc/Kconfig  |5 +
>>  drivers/pci/dwc/Makefile |1 +
>>  drivers/pci/dwc/pcie-designware-ep.c |  342 
>> ++
>>  drivers/pci/dwc/pcie-designware.c|   51 +
>>  drivers/pci/dwc/pcie-designware.h|   72 +++
>>  5 files changed, 471 insertions(+)
>>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>
>> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
>> index dfb8a69..00335c7 100644
>> --- a/drivers/pci/dwc/Kconfig
>> +++ b/drivers/pci/dwc/Kconfig
>> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>>  depends on PCI_MSI_IRQ_DOMAIN
>>  select PCIE_DW
>>  
>> +config PCIE_DW_EP
>> +bool
>> +depends on PCI_ENDPOINT
>> +select PCIE_DW
>> +
>>  config PCI_DRA7XX
>>  bool "TI DRA7xx PCIe controller"
>>  depends on PCI
>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
>> index a2df13c..b38425d 100644
>> --- a/drivers/pci/dwc/Makefile
>> +++ b/drivers/pci/dwc/Makefile
>> @@ -1,5 +1,6 @@
>>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
>> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
>> b/drivers/pci/dwc/pcie-designware-ep.c
>> new file mode 100644
>> index 000..e465c5e
>> --- /dev/null
>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>> @@ -0,0 +1,342 @@
>> +/**
>> + * Synopsys Designware PCIe Endpoint controller driver
>> + *
>> + * Copyright (C) 2017 Texas Instruments
>> + * Author: Kishon Vijay Abraham I 
>> + *
>> + * This program is free software: you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 of
>> + * the License as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see 
>> >  >.
>> + */
>> +
>> +#include 
>> +
>> +#include "pcie-designware.h"
>> +#include 
>> +#include 
>> +
>> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
>> +{
>> +struct pci_epc *epc = ep->epc;
>> +struct pci_epf *epf;
>> +
>> +list_for_each_entry(epf, >pci_epf, list)
>> +pci_epf_linkup(epf);
>> +}
>> +
>> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
>> +{
>> +u32 reg;
>> +
>> +reg = PCI_BASE_ADDRESS_0 + (4 * bar);
>> +dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
>> +dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
>> +}
>> +
>> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
>> +   struct pci_epf_header *hdr)
>> +{
>> +struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>> +struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> +void __iomem *base = pci->dbi_base;
>> +
>> +dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
>> +dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
>> +dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
>> +dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
>> +dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
>> +  hdr->subclass_code | hdr->baseclass_code << 8);
>> +dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
>> +  hdr->cache_line_size);
>> +dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
>> +  hdr->subsys_vendor_id);
>> +dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
>> +dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
>> +  hdr->interrupt_pin);
>> +
>> +return 0;
>> +}
>> +
>> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
>> +  dma_addr_t cpu_addr,
>> +  enum 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I 
>> ---
>>  drivers/pci/dwc/Kconfig  |5 +
>>  drivers/pci/dwc/Makefile |1 +
>>  drivers/pci/dwc/pcie-designware-ep.c |  342 
>> ++
>>  drivers/pci/dwc/pcie-designware.c|   51 +
>>  drivers/pci/dwc/pcie-designware.h|   72 +++
>>  5 files changed, 471 insertions(+)
>>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>
>> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
>> index dfb8a69..00335c7 100644
>> --- a/drivers/pci/dwc/Kconfig
>> +++ b/drivers/pci/dwc/Kconfig
>> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>>  depends on PCI_MSI_IRQ_DOMAIN
>>  select PCIE_DW
>>  
>> +config PCIE_DW_EP
>> +bool
>> +depends on PCI_ENDPOINT
>> +select PCIE_DW
>> +
>>  config PCI_DRA7XX
>>  bool "TI DRA7xx PCIe controller"
>>  depends on PCI
>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
>> index a2df13c..b38425d 100644
>> --- a/drivers/pci/dwc/Makefile
>> +++ b/drivers/pci/dwc/Makefile
>> @@ -1,5 +1,6 @@
>>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
>> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
>> b/drivers/pci/dwc/pcie-designware-ep.c
>> new file mode 100644
>> index 000..e465c5e
>> --- /dev/null
>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>> @@ -0,0 +1,342 @@
>> +/**
>> + * Synopsys Designware PCIe Endpoint controller driver
>> + *
>> + * Copyright (C) 2017 Texas Instruments
>> + * Author: Kishon Vijay Abraham I 
>> + *
>> + * This program is free software: you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 of
>> + * the License as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program.  If not, see 
>> >  >.
>> + */
>> +
>> +#include 
>> +
>> +#include "pcie-designware.h"
>> +#include 
>> +#include 
>> +
>> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
>> +{
>> +struct pci_epc *epc = ep->epc;
>> +struct pci_epf *epf;
>> +
>> +list_for_each_entry(epf, >pci_epf, list)
>> +pci_epf_linkup(epf);
>> +}
>> +
>> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
>> +{
>> +u32 reg;
>> +
>> +reg = PCI_BASE_ADDRESS_0 + (4 * bar);
>> +dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
>> +dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
>> +}
>> +
>> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
>> +   struct pci_epf_header *hdr)
>> +{
>> +struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>> +struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>> +void __iomem *base = pci->dbi_base;
>> +
>> +dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
>> +dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
>> +dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
>> +dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
>> +dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
>> +  hdr->subclass_code | hdr->baseclass_code << 8);
>> +dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
>> +  hdr->cache_line_size);
>> +dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
>> +  hdr->subsys_vendor_id);
>> +dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
>> +dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
>> +  hdr->interrupt_pin);
>> +
>> +return 0;
>> +}
>> +
>> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
>> +  dma_addr_t cpu_addr,
>> +  enum dw_pcie_as_type as_type)
>> +{
>> +

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>
>>> Hi Kishon,
>>>
> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?

 Yes of course, I will send you the definition soon.
>>>
>>> As promissed here is the definition for Inbound:
>>>
>>> +/* register address builder */
>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)\
>>> +   ((0x3 << 20) | (region << 9) |  \
>>> +   (0x1 << 8) | (register << 2))
>>
>> Cool, thanks!
> 
> No problem! If you have doubts, please let me know.

Okay, so this looks slightly different than the outbound macro since it takes
the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
returns the offset which was used like
dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);

How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?

Thanks
Kishon

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>>
>>> Hi Kishon,
>>>
> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?

 Yes of course, I will send you the definition soon.
>>>
>>> As promissed here is the definition for Inbound:
>>>
>>> +/* register address builder */
>>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)\
>>> +   ((0x3 << 20) | (region << 9) |  \
>>> +   (0x1 << 8) | (register << 2))
>>
>> Cool, thanks!
> 
> No problem! If you have doubts, please let me know.

Okay, so this looks slightly different than the outbound macro since it takes
the register argument. In the case of outbound PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
returns the offset which was used like
dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);

How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?

Thanks
Kishon

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> 
> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>> Hi,
>>>
>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:

 Hi Kishon,

>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>
> Yes of course, I will send you the definition soon.

 As promissed here is the definition for Inbound:

 +/* register address builder */
 +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)   \
 +  ((0x3 << 20) | (region << 9) |  \
 +  (0x1 << 8) | (register << 2))
>>>
>>> Cool, thanks!
>>
>> No problem! If you have doubts, please let me know.
> 
> Okay, so this looks slightly different than the outbound macro since it takes
> the register argument. In the case of outbound 
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
> returns the offset which was used like
> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
> 
> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?

My original way was this one:

+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register)   \
+   ((0x3 << 20) | (region << 9) |  \
+   (register << 2))

Bjorn then converted to offset:

#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)  ((0x3 << 20) | (region << 9))

and applied the <<2 shift to the ATU registers.

So you can use:

#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
((0x3 << 20) | (region << 9) |  \
(0x1 << 8)

Thanks.

> 
> Thanks
> Kishon
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> 
> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>> Hi,
>>>
>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:

 Hi Kishon,

>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>
> Yes of course, I will send you the definition soon.

 As promissed here is the definition for Inbound:

 +/* register address builder */
 +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)   \
 +  ((0x3 << 20) | (region << 9) |  \
 +  (0x1 << 8) | (register << 2))
>>>
>>> Cool, thanks!
>>
>> No problem! If you have doubts, please let me know.
> 
> Okay, so this looks slightly different than the outbound macro since it takes
> the register argument. In the case of outbound 
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
> returns the offset which was used like
> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
> 
> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?

My original way was this one:

+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register)   \
+   ((0x3 << 20) | (region << 9) |  \
+   (register << 2))

Bjorn then converted to offset:

#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)  ((0x3 << 20) | (region << 9))

and applied the <<2 shift to the ATU registers.

So you can use:

#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
((0x3 << 20) | (region << 9) |  \
(0x1 << 8)

Thanks.

> 
> Thanks
> Kishon
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 3:32 PM de 3/8/2017, Joao Pinto escreveu:
> Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
 Hi,

 On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>
> Hi Kishon,
>
>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>
>> Yes of course, I will send you the definition soon.
>
> As promissed here is the definition for Inbound:
>
> +/* register address builder */
> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)  \
> + ((0x3 << 20) | (region << 9) |  \
> + (0x1 << 8) | (register << 2))

 Cool, thanks!
>>>
>>> No problem! If you have doubts, please let me know.
>>
>> Okay, so this looks slightly different than the outbound macro since it takes
>> the register argument. In the case of outbound 
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
>> returns the offset which was used like
>> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
>>
>> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?
> 
> My original way was this one:
> 
> +/* Register address builder */
> +#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register) \
> + ((0x3 << 20) | (region << 9) |  \
> + (register << 2))
> 
> Bjorn then converted to offset:
> 
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)  ((0x3 << 20) | (region << 
> 9))
> 
> and applied the <<2 shift to the ATU registers.
> 
> So you can use:
> 
> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)   \
>   ((0x3 << 20) | (region << 9) |  \
>   (0x1 << 8)
> 

This one has the right name :)

#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region, register)   \
((0x3 << 20) | (region << 9) |  \
(0x1 << 8)


> Thanks.
> 
>>
>> Thanks
>> Kishon
>>
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 3:32 PM de 3/8/2017, Joao Pinto escreveu:
> Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
 Hi,

 On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>
> Hi Kishon,
>
>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>
>> Yes of course, I will send you the definition soon.
>
> As promissed here is the definition for Inbound:
>
> +/* register address builder */
> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)  \
> + ((0x3 << 20) | (region << 9) |  \
> + (0x1 << 8) | (register << 2))

 Cool, thanks!
>>>
>>> No problem! If you have doubts, please let me know.
>>
>> Okay, so this looks slightly different than the outbound macro since it takes
>> the register argument. In the case of outbound 
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
>> returns the offset which was used like
>> dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
>>
>> How should the value from PCIE_GET_ATU_INB_UNR_REG_ADDR be used?
> 
> My original way was this one:
> 
> +/* Register address builder */
> +#define PCIE_GET_ATU_OUTB_UNR_REG_ADDR(region, register) \
> + ((0x3 << 20) | (region << 9) |  \
> + (register << 2))
> 
> Bjorn then converted to offset:
> 
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)  ((0x3 << 20) | (region << 
> 9))
> 
> and applied the <<2 shift to the ATU registers.
> 
> So you can use:
> 
> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)   \
>   ((0x3 << 20) | (region << 9) |  \
>   (0x1 << 8)
> 

This one has the right name :)

#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region, register)   \
((0x3 << 20) | (region << 9) |  \
(0x1 << 8)


> Thanks.
> 
>>
>> Thanks
>> Kishon
>>
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
> 
> Hi Kishon,
> 
>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>
>> Yes of course, I will send you the definition soon.
> 
> As promissed here is the definition for Inbound:
> 
> +/* register address builder */
> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)  \
> + ((0x3 << 20) | (region << 9) |  \
> + (0x1 << 8) | (register << 2))

Cool, thanks!

-Kishon
> 
> Thanks,
> Joao
> 
>>
>> Thanks,
>> Joao
>>
>>>
>>> Thanks
>>> Kishon
>>>
>>
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
> 
> Hi Kishon,
> 
>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>
>> Yes of course, I will send you the definition soon.
> 
> As promissed here is the definition for Inbound:
> 
> +/* register address builder */
> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)  \
> + ((0x3 << 20) | (region << 9) |  \
> + (0x1 << 8) | (register << 2))

Cool, thanks!

-Kishon
> 
> Thanks,
> Joao
> 
>>
>> Thanks,
>> Joao
>>
>>>
>>> Thanks
>>> Kishon
>>>
>>
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> 
> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
 Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
 PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>
>>> Yes of course, I will send you the definition soon.
>>
>> As promissed here is the definition for Inbound:
>>
>> +/* register address builder */
>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>> +((0x3 << 20) | (region << 9) |  \
>> +(0x1 << 8) | (register << 2))
> 
> Cool, thanks!

No problem! If you have doubts, please let me know.

Thanks,
Joao

> 
> -Kishon
>>
>> Thanks,
>> Joao
>>
>>>
>>> Thanks,
>>> Joao
>>>

 Thanks
 Kishon

>>>
>>

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
> 
> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
 Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
 PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>>>
>>> Yes of course, I will send you the definition soon.
>>
>> As promissed here is the definition for Inbound:
>>
>> +/* register address builder */
>> +#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>> +((0x3 << 20) | (region << 9) |  \
>> +(0x1 << 8) | (register << 2))
> 
> Cool, thanks!

No problem! If you have doubts, please let me know.

Thanks,
Joao

> 
> -Kishon
>>
>> Thanks,
>> Joao
>>
>>>
>>> Thanks,
>>> Joao
>>>

 Thanks
 Kishon

>>>
>>

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Hi Kishon,

>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
> 
> Yes of course, I will send you the definition soon.

As promissed here is the definition for Inbound:

+/* register address builder */
+#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)\
+   ((0x3 << 20) | (region << 9) |  \
+   (0x1 << 8) | (register << 2))

Thanks,
Joao

> 
> Thanks,
> Joao
> 
>>
>> Thanks
>> Kishon
>>
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Hi Kishon,

>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
> 
> Yes of course, I will send you the definition soon.

As promissed here is the definition for Inbound:

+/* register address builder */
+#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register)\
+   ((0x3 << 20) | (region << 9) |  \
+   (0x1 << 8) | (register << 2))

Thanks,
Joao

> 
> Thanks,
> Joao
> 
>>
>> Thanks
>> Kishon
>>
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi Joao,

On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I 
>> ---
>>  drivers/pci/dwc/Kconfig  |5 +
>>  drivers/pci/dwc/Makefile |1 +
>>  drivers/pci/dwc/pcie-designware-ep.c |  342 
>> ++
>>  drivers/pci/dwc/pcie-designware.c|   51 +
>>  drivers/pci/dwc/pcie-designware.h|   72 +++
>>  5 files changed, 471 insertions(+)
>>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>



>> diff --git a/drivers/pci/dwc/pcie-designware.c 
>> b/drivers/pci/dwc/pcie-designware.c
>> index 686945d..49b28c8 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int 
>> index, int type,
>>  dev_err(pci->dev, "iATU is not being enabled\n");
>>  }
>>  
>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>> + u64 cpu_addr, enum dw_pcie_as_type as_type)
>> +{
>> +int type;
>> +void __iomem *base = pci->dbi_base;
>> +
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>> +  PCIE_ATU_REGION_INBOUND | index);
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>> +  lower_32_bits(cpu_addr));
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>> +  upper_32_bits(cpu_addr));
>> +
>> +switch (as_type) {
>> +case DW_PCIE_AS_MEM:
>> +type = PCIE_ATU_TYPE_MEM;
>> +break;
>> +case DW_PCIE_AS_IO:
>> +type = PCIE_ATU_TYPE_IO;
>> +break;
>> +default:
>> +return -EINVAL;
>> +}
>> +
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>> +  PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>> +return 0;
>> +}
>> +
> 
> This Atu programming is for PCI Cores <= 4.70. Please follow the same 
> approach as:
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/tree/drivers/pci/dwc/pcie-designware.c?h=pci/host-designware#n95

Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?

Thanks
Kishon

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi Joao,

On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Add endpoint mode support to designware driver. This uses the
>> EP Core layer introduced recently to add endpoint mode support.
>> *Any* function driver can now use this designware device
>> in order to achieve the EP functionality.
>>
>> Signed-off-by: Kishon Vijay Abraham I 
>> ---
>>  drivers/pci/dwc/Kconfig  |5 +
>>  drivers/pci/dwc/Makefile |1 +
>>  drivers/pci/dwc/pcie-designware-ep.c |  342 
>> ++
>>  drivers/pci/dwc/pcie-designware.c|   51 +
>>  drivers/pci/dwc/pcie-designware.h|   72 +++
>>  5 files changed, 471 insertions(+)
>>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>



>> diff --git a/drivers/pci/dwc/pcie-designware.c 
>> b/drivers/pci/dwc/pcie-designware.c
>> index 686945d..49b28c8 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int 
>> index, int type,
>>  dev_err(pci->dev, "iATU is not being enabled\n");
>>  }
>>  
>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>> + u64 cpu_addr, enum dw_pcie_as_type as_type)
>> +{
>> +int type;
>> +void __iomem *base = pci->dbi_base;
>> +
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>> +  PCIE_ATU_REGION_INBOUND | index);
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>> +  lower_32_bits(cpu_addr));
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>> +  upper_32_bits(cpu_addr));
>> +
>> +switch (as_type) {
>> +case DW_PCIE_AS_MEM:
>> +type = PCIE_ATU_TYPE_MEM;
>> +break;
>> +case DW_PCIE_AS_IO:
>> +type = PCIE_ATU_TYPE_IO;
>> +break;
>> +default:
>> +return -EINVAL;
>> +}
>> +
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>> +dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>> +  PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>> +return 0;
>> +}
>> +
> 
> This Atu programming is for PCI Cores <= 4.70. Please follow the same 
> approach as:
> https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/tree/drivers/pci/dwc/pcie-designware.c?h=pci/host-designware#n95

Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?

Thanks
Kishon

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Hi Kishon,

Às 5:18 AM de 3/7/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
> 
> On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Add endpoint mode support to designware driver. This uses the
>>> EP Core layer introduced recently to add endpoint mode support.
>>> *Any* function driver can now use this designware device
>>> in order to achieve the EP functionality.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I 
>>> ---
>>>  drivers/pci/dwc/Kconfig  |5 +
>>>  drivers/pci/dwc/Makefile |1 +
>>>  drivers/pci/dwc/pcie-designware-ep.c |  342 
>>> ++
>>>  drivers/pci/dwc/pcie-designware.c|   51 +
>>>  drivers/pci/dwc/pcie-designware.h|   72 +++
>>>  5 files changed, 471 insertions(+)
>>>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>>
> 
> 
> 
>>> diff --git a/drivers/pci/dwc/pcie-designware.c 
>>> b/drivers/pci/dwc/pcie-designware.c
>>> index 686945d..49b28c8 100644
>>> --- a/drivers/pci/dwc/pcie-designware.c
>>> +++ b/drivers/pci/dwc/pcie-designware.c
>>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 
>>> int index, int type,
>>> dev_err(pci->dev, "iATU is not being enabled\n");
>>>  }
>>>  
>>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>>> +u64 cpu_addr, enum dw_pcie_as_type as_type)
>>> +{
>>> +   int type;
>>> +   void __iomem *base = pci->dbi_base;
>>> +
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>>> + PCIE_ATU_REGION_INBOUND | index);
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>>> + lower_32_bits(cpu_addr));
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>>> + upper_32_bits(cpu_addr));
>>> +
>>> +   switch (as_type) {
>>> +   case DW_PCIE_AS_MEM:
>>> +   type = PCIE_ATU_TYPE_MEM;
>>> +   break;
>>> +   case DW_PCIE_AS_IO:
>>> +   type = PCIE_ATU_TYPE_IO;
>>> +   break;
>>> +   default:
>>> +   return -EINVAL;
>>> +   }
>>> +
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>>> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>>> +   return 0;
>>> +}
>>> +
>>
>> This Atu programming is for PCI Cores <= 4.70. Please follow the same 
>> approach as:
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_cgit_linux_kernel_git_helgaas_pci.git_tree_drivers_pci_dwc_pcie-2Ddesignware.c-3Fh-3Dpci_host-2Ddesignware-23n95=DwID-g=DPL6_X_6JkXFx7AXWqB0tg=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0=MqqHFJBR0jj9ZQILcUJEd-CQkTihuOSf69e-XxZJvRs=fY5N7Mt9iszsAI04DPm-cSC6cSE5P2axHUFQ9GOx-2A=
>>  
> 
> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?

Yes of course, I will send you the definition soon.

Thanks,
Joao

> 
> Thanks
> Kishon
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Hi Kishon,

Às 5:18 AM de 3/7/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
> 
> On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Add endpoint mode support to designware driver. This uses the
>>> EP Core layer introduced recently to add endpoint mode support.
>>> *Any* function driver can now use this designware device
>>> in order to achieve the EP functionality.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I 
>>> ---
>>>  drivers/pci/dwc/Kconfig  |5 +
>>>  drivers/pci/dwc/Makefile |1 +
>>>  drivers/pci/dwc/pcie-designware-ep.c |  342 
>>> ++
>>>  drivers/pci/dwc/pcie-designware.c|   51 +
>>>  drivers/pci/dwc/pcie-designware.h|   72 +++
>>>  5 files changed, 471 insertions(+)
>>>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
>>>
> 
> 
> 
>>> diff --git a/drivers/pci/dwc/pcie-designware.c 
>>> b/drivers/pci/dwc/pcie-designware.c
>>> index 686945d..49b28c8 100644
>>> --- a/drivers/pci/dwc/pcie-designware.c
>>> +++ b/drivers/pci/dwc/pcie-designware.c
>>> @@ -173,6 +173,57 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 
>>> int index, int type,
>>> dev_err(pci->dev, "iATU is not being enabled\n");
>>>  }
>>>  
>>> +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>>> +u64 cpu_addr, enum dw_pcie_as_type as_type)
>>> +{
>>> +   int type;
>>> +   void __iomem *base = pci->dbi_base;
>>> +
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
>>> + PCIE_ATU_REGION_INBOUND | index);
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
>>> + lower_32_bits(cpu_addr));
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
>>> + upper_32_bits(cpu_addr));
>>> +
>>> +   switch (as_type) {
>>> +   case DW_PCIE_AS_MEM:
>>> +   type = PCIE_ATU_TYPE_MEM;
>>> +   break;
>>> +   case DW_PCIE_AS_IO:
>>> +   type = PCIE_ATU_TYPE_IO;
>>> +   break;
>>> +   default:
>>> +   return -EINVAL;
>>> +   }
>>> +
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
>>> +   dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE |
>>> + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
>>> +   return 0;
>>> +}
>>> +
>>
>> This Atu programming is for PCI Cores <= 4.70. Please follow the same 
>> approach as:
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_cgit_linux_kernel_git_helgaas_pci.git_tree_drivers_pci_dwc_pcie-2Ddesignware.c-3Fh-3Dpci_host-2Ddesignware-23n95=DwID-g=DPL6_X_6JkXFx7AXWqB0tg=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0=MqqHFJBR0jj9ZQILcUJEd-CQkTihuOSf69e-XxZJvRs=fY5N7Mt9iszsAI04DPm-cSC6cSE5P2axHUFQ9GOx-2A=
>>  
> 
> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?

Yes of course, I will send you the definition soon.

Thanks,
Joao

> 
> Thanks
> Kishon
> 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/dwc/Kconfig  |5 +
>  drivers/pci/dwc/Makefile |1 +
>  drivers/pci/dwc/pcie-designware-ep.c |  342 
> ++
>  drivers/pci/dwc/pcie-designware.c|   51 +
>  drivers/pci/dwc/pcie-designware.h|   72 +++
>  5 files changed, 471 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>   depends on PCI_MSI_IRQ_DOMAIN
>  select PCIE_DW
>  
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
>  config PCI_DRA7XX
>   bool "TI DRA7xx PCIe controller"
>   depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
> b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see 
>   >.
> + */
> +
> +#include 
> +
> +#include "pcie-designware.h"
> +#include 
> +#include 
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, >pci_epf, list)
> + pci_epf_linkup(epf);
> +}
> +
> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> +{
> + u32 reg;
> +
> + reg = PCI_BASE_ADDRESS_0 + (4 * bar);
> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
> +}
> +
> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
> +struct pci_epf_header *hdr)
> +{
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + void __iomem *base = pci->dbi_base;
> +
> + dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
> + dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
> + dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
> +   hdr->subclass_code | hdr->baseclass_code << 8);
> + dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
> +   hdr->cache_line_size);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
> +   hdr->subsys_vendor_id);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
> + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
> +   hdr->interrupt_pin);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
> +   dma_addr_t cpu_addr,
> +   enum dw_pcie_as_type as_type)
> +{
> + int ret;
> + u32 free_win;
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +
> + free_win = 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/dwc/Kconfig  |5 +
>  drivers/pci/dwc/Makefile |1 +
>  drivers/pci/dwc/pcie-designware-ep.c |  342 
> ++
>  drivers/pci/dwc/pcie-designware.c|   51 +
>  drivers/pci/dwc/pcie-designware.h|   72 +++
>  5 files changed, 471 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>   depends on PCI_MSI_IRQ_DOMAIN
>  select PCIE_DW
>  
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
>  config PCI_DRA7XX
>   bool "TI DRA7xx PCIe controller"
>   depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
> b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see 
>   >.
> + */
> +
> +#include 
> +
> +#include "pcie-designware.h"
> +#include 
> +#include 
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, >pci_epf, list)
> + pci_epf_linkup(epf);
> +}
> +
> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> +{
> + u32 reg;
> +
> + reg = PCI_BASE_ADDRESS_0 + (4 * bar);
> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
> +}
> +
> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
> +struct pci_epf_header *hdr)
> +{
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + void __iomem *base = pci->dbi_base;
> +
> + dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
> + dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
> + dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
> +   hdr->subclass_code | hdr->baseclass_code << 8);
> + dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
> +   hdr->cache_line_size);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
> +   hdr->subsys_vendor_id);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
> + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
> +   hdr->interrupt_pin);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
> +   dma_addr_t cpu_addr,
> +   enum dw_pcie_as_type as_type)
> +{
> + int ret;
> + u32 free_win;
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +
> + free_win = find_first_zero_bit(>ib_window_map,
> + 

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Friday 17 February 2017 03:20 PM, Kishon Vijay Abraham I wrote:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/dwc/Kconfig  |5 +
>  drivers/pci/dwc/Makefile |1 +
>  drivers/pci/dwc/pcie-designware-ep.c |  342 
> ++
>  drivers/pci/dwc/pcie-designware.c|   51 +
>  drivers/pci/dwc/pcie-designware.h|   72 +++
>  5 files changed, 471 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>   depends on PCI_MSI_IRQ_DOMAIN
>  select PCIE_DW
>  
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
>  config PCI_DRA7XX
>   bool "TI DRA7xx PCIe controller"
>   depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
> b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +
> +#include "pcie-designware.h"
> +#include 
> +#include 
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, >pci_epf, list)
> + pci_epf_linkup(epf);

Just notices, the right place to use this list should be pci-epc-core. Will fix
this in the next revision.

Thanks
Kishon

Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Friday 17 February 2017 03:20 PM, Kishon Vijay Abraham I wrote:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/dwc/Kconfig  |5 +
>  drivers/pci/dwc/Makefile |1 +
>  drivers/pci/dwc/pcie-designware-ep.c |  342 
> ++
>  drivers/pci/dwc/pcie-designware.c|   51 +
>  drivers/pci/dwc/pcie-designware.h|   72 +++
>  5 files changed, 471 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>   depends on PCI_MSI_IRQ_DOMAIN
>  select PCIE_DW
>  
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
>  config PCI_DRA7XX
>   bool "TI DRA7xx PCIe controller"
>   depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
> b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +
> +#include "pcie-designware.h"
> +#include 
> +#include 
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, >pci_epf, list)
> + pci_epf_linkup(epf);

Just notices, the right place to use this list should be pci-epc-core. Will fix
this in the next revision.

Thanks
Kishon