On Fri, Aug 02, 2024 at 10:57:54PM GMT, Mark Brown wrote:
> Currently the get-reg-list test uses directly specified numeric values to
> define system registers to validate. Since we already have a macro which
> allows us to use the generated system register definitions from the main
> kernel easily
On Mon, Jul 22, 2024 at 02:14:44PM GMT, Charlie Jenkins wrote:
> On Mon, Jul 22, 2024 at 01:47:29PM -0500, Andrew Jones wrote:
> > On Fri, Jul 19, 2024 at 09:19:07AM GMT, Charlie Jenkins wrote:
> > > Overhaul the riscv vector tests to use kselftest_harness to help the
> >
On Fri, Jul 19, 2024 at 09:19:07AM GMT, Charlie Jenkins wrote:
> Overhaul the riscv vector tests to use kselftest_harness to help the
> test cases correctly report the results and decouple the individual test
> cases from each other. With this refactoring, only run the test cases is
> vector is rep
eg_list *vcpu_configs[] = {
> &config_smstateen,
> &config_sscofpmf,
> &config_sstc,
> + &config_svade,
> + &config_svadu,
> &config_svinval,
> &config_svnapot,
> &config_svpbmt,
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
);
> KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
> @@ -987,6 +990,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_h,
> &config_smstateen,
> &config_sstc,
> + &config_svadu,
> &config_svinval,
> &config_svnapot,
> &config_svpbmt,
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
On Wed, May 01, 2024 at 02:54:32PM GMT, Manali Shukla wrote:
> From: Manali Shukla
>
> The interface is used to read the data values of a specified vcpu stat
> from the currenly available binary stats interface.
>
> Signed-off-by: Manali Shukla
> ---
> .../testing/selftests/kvm/include/kvm_uti
> -
> - test_add_max_memory_regions();
> -
> -#ifdef __x86_64__
> - if (kvm_has_cap(KVM_CAP_GUEST_MEMFD) &&
> - (kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SW_PROTECTED_VM))) {
> - test_add_private_memory_region();
> - test_add_overlapping_private_memory_regions();
> - } else {
> - pr_info("Skipping tests for KVM_MEM_GUEST_MEMFD memory
> regions\n");
> - }
> -
> if (argc > 1)
> loops = atoi_positive("Number of iterations", argv[1]);
> else
> loops = 10;
>
> - pr_info("Testing MOVE of in-use region, %d loops\n", loops);
> - for (i = 0; i < loops; i++)
> - test_move_memory_region();
> -
> - pr_info("Testing DELETE of in-use region, %d loops\n", loops);
> - for (i = 0; i < loops; i++)
> - test_delete_memory_region();
> -#endif
> -
> - return 0;
> + return test_harness_run(argc, argv);
> }
> --
> 2.44.0
>
Reviewed-by: Andrew Jones
Thanks,
drew
.gitignore which ignores everything except the code. See
tools/testing/selftests/kvm/.gitignore
But, until (if at all) we go that way, we can do what this patch does,
Reviewed-by: Andrew Jones
Thanks,
drew
On Tue, Apr 23, 2024 at 12:15:47PM -0700, Sean Christopherson wrote:
...
> I almost wonder if we should just pick a prefix that's less obviously
> connected
> to KVM and/or selftests, but unique and short.
>
How about kvmsft_ ? It's based on the ksft_ prefix of kselftest.h. Maybe
it's too close t
On Tue, Apr 23, 2024 at 07:56:01AM -0700, Sean Christopherson wrote:
> +others
>
> On Tue, Apr 23, 2024, Markus Elfring wrote:
> > …
> > > This patch will add the malloc failure checking
> > …
> >
> > * Please use a corresponding imperative wording for the change description.
> >
> > * Would you
On Tue, Apr 23, 2024 at 02:03:29PM +0500, Muhammad Usama Anjum wrote:
...
> > + pr_info("Usage: %s [-h] [-d ]\n", name);
> A little weird that we have pr_info named helper to print logs when it is a
> userspace application, not kernel code. I'll check it in the source who
> added it to the KVM te
On Tue, Apr 16, 2024 at 01:31:27AM -0700, Atish Patra wrote:
> On 4/15/24 06:06, Andrew Jones wrote:
> > On Wed, Apr 10, 2024 at 05:07:35PM -0700, Atish Patra wrote:
> > > As per the SBI specification, minor version is encoded in the
> > > lower 24 bits only. Make s
ll events or all ISA extensions.
>
> The commandline option allows user to disable particular test if they
> want to.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Atish Patra
> ---
> .../selftests/kvm/riscv/sbi_pmu_test.c| 77 ---
> 1 file
/kvm/riscv/sbi_pmu_test.c| 113 ++
> 1 file changed, 113 insertions(+)
>
Reviewed-by: Andrew Jones
On Wed, Apr 10, 2024 at 05:07:50PM -0700, Atish Patra wrote:
> Verify PMU snapshot functionality by setting up the shared memory
> correctly and reading the counter values from the shared memory
> instead of the CSR.
>
> Reviewed-by: Andrew Jones
> Reviewed-by: Anup Patel
>
.../selftests/kvm/riscv/sbi_pmu_test.c| 369 ++
> 2 files changed, 370 insertions(+)
> create mode 100644 tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
>
Reviewed-by: Andrew Jones
| 1 +
> arch/riscv/kvm/aia.c | 5 ++
> arch/riscv/kvm/vcpu.c | 15 --
> arch/riscv/kvm/vcpu_onereg.c | 6 +++
> arch/riscv/kvm/vcpu_pmu.c | 68 +--
> 7 files changed, 93 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones
ude/asm/kvm_vcpu_pmu.h | 7 ++
> arch/riscv/kvm/vcpu_pmu.c | 121 +-
> arch/riscv/kvm/vcpu_sbi_pmu.c | 3 +
> 3 files changed, 130 insertions(+), 1 deletion(-)
>
Reviewed-by: Andrew Jones
ddr = page_to_virt(snapshot_page);
> + cpu_hw_evt->snapshot_addr_phys = page_to_phys(snapshot_page);
> + }
> +
> + return 0;
> +}
> +
> +static int pmu_sbi_snapshot_disable(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, -1,
> + -1, 0, 0, 0, 0);
The SBI_SHMEM_DISABLE patch got moved in front of this patch, but looks
like it was forgotten to apply it.
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
er
have them around all the major bits before the OR. We don't need the
parentheses around the major bits, since shift has higher precedence
than OR, but I'd probably keep them.
Otherwise,
Reviewed-by: Andrew Jones
> }
>
> int sbi_err_map_linux_errno(int err);
> --
> 2.34.1
>
(CSR_SSCOUNTOVF),\
> + "csrr %0, " __stringify(CSR_SCOUNTOVF), \
> "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
> THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
> CONFIG_ERRATA_THEAD_PMU,\
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Wed, Apr 10, 2024 at 03:29:21PM -0700, Atish Patra wrote:
> On 4/4/24 04:52, Andrew Jones wrote:
> > On Wed, Apr 03, 2024 at 01:04:35AM -0700, Atish Patra wrote:
...
> > > +static int pmu_sbi_snapshot_disable(void)
> > > +{
> > > + struct sbiret ret;
> &g
On Wed, Apr 10, 2024 at 03:44:32PM -0700, Atish Patra wrote:
> On 4/4/24 05:16, Andrew Jones wrote:
> > On Mon, Apr 01, 2024 at 03:37:01PM -0700, Atish Patra wrote:
> > > On Sat, Mar 2, 2024 at 12:16 AM Andrew Jones
> > > wrote:
> > > >
> > > &
On Wed, Apr 10, 2024 at 12:28:08AM -0700, Atish Patra wrote:
>
> On 4/10/24 00:10, Andrew Jones wrote:
> > On Tue, Apr 09, 2024 at 03:52:40PM -0700, Atish Patra wrote:
> > > On 4/5/24 06:11, Andrew Jones wrote:
> > > > On Wed, Apr 03, 2024 at 01
On Tue, Apr 09, 2024 at 05:11:31PM -0700, Atish Patra wrote:
> On 4/5/24 05:05, Andrew Jones wrote:
> > On Tue, Apr 02, 2024 at 01:33:10AM -0700, Atish Patra wrote:
> > ...
> > > > but it should be possible for the VMM to disable this extension in the
> > > >
On Tue, Apr 09, 2024 at 03:52:40PM -0700, Atish Patra wrote:
> On 4/5/24 06:11, Andrew Jones wrote:
> > On Wed, Apr 03, 2024 at 01:04:50AM -0700, Atish Patra wrote:
...
> > > + probe = guest_sbi_probe_extension(SBI_EXT_PMU, &out_val);
> > > + GUEST_ASSERT(probe &
On Mon, Apr 08, 2024 at 05:37:19PM -0700, Atish Patra wrote:
> On 4/5/24 05:50, Andrew Jones wrote:
> > On Wed, Apr 03, 2024 at 01:04:49AM -0700, Atish Patra wrote:
> > ...
> > > +static void test_pmu_basic_sanity(void)
> > > +{
> > > + long out_val = 0;
On Mon, Apr 08, 2024 at 01:19:39PM +0200, Clément Léger wrote:
>
>
> On 08/04/2024 13:03, Andrew Jones wrote:
> > On Mon, Apr 08, 2024 at 10:01:12AM +0200, Clément Léger wrote:
> >>
> >>
> >> On 05/04/2024 19:33, Deepak Gupta wrote:
> >>> On
0 insertions(+)
>
> --
> 2.43.0
For the series,
Reviewed-by: Andrew Jones
On Mon, Apr 08, 2024 at 10:01:12AM +0200, Clément Léger wrote:
>
>
> On 05/04/2024 19:33, Deepak Gupta wrote:
> > On Fri, Apr 5, 2024 at 8:26 AM Andrew Jones wrote:
> >>
> >> On Thu, Apr 04, 2024 at 12:32:46PM +0200, Clément Léger wrote:
> >>> The Zi
On Fri, Mar 29, 2024 at 10:31:10AM +, Conor Dooley wrote:
> On Fri, Mar 29, 2024 at 05:26:18PM +0800, Max Hsu wrote:
> > The mcontext/hcontext/scontext CSRs are optional in the Sdtrig extension,
> > to prevent RW operations to the missing CSRs, which will cause
> > illegal instructions.
> >
>
On Thu, Apr 04, 2024 at 12:32:46PM +0200, Clément Léger wrote:
> The Zimop ISA extension was ratified recently. This series adds support
> for parsing it from riscv,isa, hwprobe export and kvm support for
> Guest/VM.
I'm not sure we need this. Zimop by itself isn't useful, so I don't know
if we ne
dler(vm, guest_irq_handler);
> +
> + vcpu_init_vector_tables(vcpu);
> + /* Initialize guest timer frequency. */
> + vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency), &timer_freq);
> + sync_global_to_guest(vm, timer_freq);
> +
> + run_vcpu(vcpu);
> +
> + test_vm_destroy(vm);
> +}
> +
> int main(void)
> {
> pr_info("SBI PMU basic test : starting\n");
> @@ -463,5 +574,8 @@ int main(void)
> test_vm_events_snapshot_test(test_pmu_events_snaphost);
> pr_info("SBI PMU event verification with snapshot test : PASS\n");
>
> + test_vm_events_overflow(test_pmu_events_overflow);
> + pr_info("SBI PMU event verification with overflow test : PASS\n");
> +
> return 0;
> }
> --
> 2.34.1
>
Other than the command line option idea,
Reviewed-by: Andrew Jones
Thanks,
drew
sync_global_to_guest(vcpu->vm, snapshot_gva);
> + sync_global_to_guest(vcpu->vm, snapshot_gpa);
> +}
> +
> +static void test_vm_events_snapshot_test(void *guest_code)
> +{
> + struct kvm_vm *vm = NULL;
> + struct kvm_vcpu *vcpu;
> +
> + vm = vm_create_with_one_vcpu(&vcpu, guest_code);
> + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU),
> +"SBI PMU not available, skipping test");
> +
> + test_vm_setup_snapshot_mem(vm, vcpu);
> +
> + run_vcpu(vcpu);
> +
> + test_vm_destroy(vm);
> +}
> +
> int main(void)
> {
> + pr_info("SBI PMU basic test : starting\n");
> test_vm_basic_test(test_pmu_basic_sanity);
> pr_info("SBI PMU basic test : PASS\n");
>
> test_vm_events_test(test_pmu_events);
> pr_info("SBI PMU event verification test : PASS\n");
>
> + test_vm_events_snapshot_test(test_pmu_events_snaphost);
> + pr_info("SBI PMU event verification with snapshot test : PASS\n");
> +
> return 0;
> }
> --
> 2.34.1
>
Since my comments are a bit out-of-scope for this patch,
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Apr 03, 2024 at 01:04:49AM -0700, Atish Patra wrote:
...
> +static void test_pmu_basic_sanity(void)
> +{
> + long out_val = 0;
> + bool probe;
> + struct sbiret ret;
> + int num_counters = 0, i;
> + union sbi_pmu_ctr_info ctrinfo;
> +
> + probe = guest_sbi_probe_exte
On Tue, Apr 02, 2024 at 01:34:54AM -0700, Atish Patra wrote:
...
> > > +static void guest_illegal_exception_handler(struct ex_regs *regs)
> > > +{
> > > + __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL,
> > > +"Unexpected exception handler %lx\n", regs->cause);
> >
> > Shoul
> +/* Flags defined for counter stop function */
> +#define SBI_PMU_STOP_FLAG_RESET BIT(0)
> +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
> +
> struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> unsigned long arg1, unsigned long arg2,
> unsigned long arg3, unsigned long arg4,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
RE(__vcpu_has_ext(vcpus[0],
> RISCV_ISA_EXT_REG(KVM_RISCV_ISA_EXT_SSTC)),
> + __TEST_REQUIRE(__vcpu_has_isa_ext(vcpus[0], KVM_RISCV_ISA_EXT_SSTC),
> "SSTC not available, skipping test\n");
>
> vm_init_vector_tables(vm);
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Wed, Apr 03, 2024 at 01:04:45AM -0700, Atish Patra wrote:
> The SBI definitions will continue to grow. Move the sbi related
> definitions to its own header file from processor.h
>
> Suggested-by: Andrew Jones
> Signed-off-by: Atish Patra
> ---
> .../selftests/kvm/incl
tdata);
> break;
> case SBI_EXT_PMU_COUNTER_FW_READ:
> - ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata);
> + ret = kvm_riscv_vcpu_pmu_fw_ctr_read(vcpu, cp->a0, retdata);
> break;
> case SBI_EXT_PMU_COUNTER_FW_READ_HI:
> if (IS_ENABLED(CONFIG_32BIT))
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
andler(struct kvm_vcpu *vcpu,
> struct kvm_run *run,
> case SBI_EXT_PMU_COUNTER_FW_READ:
> ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata);
> break;
> + case SBI_EXT_PMU_COUNTER_FW_READ_HI:
> + if (IS_ENABLED(CONFIG_32BIT))
> + ret = kvm_riscv_vcpu_pmu_fw_ctr_read_hi(vcpu, cp->a0,
> retdata);
> + else
> + retdata->out_val = 0;
> + break;
> case SBI_EXT_PMU_SNAPSHOT_SET_SHMEM:
> ret = kvm_riscv_vcpu_pmu_snapshot_set_shmem(vcpu, cp->a0,
> cp->a1, cp->a2, retdata);
> break;
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Tue, Apr 02, 2024 at 01:33:10AM -0700, Atish Patra wrote:
...
> > but it should be possible for the VMM to disable this extension in the
> > guest. We just need to change all the checks in KVM of the host's ISA
> > for RISCV_ISA_EXT_SSCOFPMF to checking the guest's ISA instead. Maybe
> > it's no
On Wed, Apr 03, 2024 at 01:04:42AM -0700, Atish Patra wrote:
> KVM enables perf for guest via counter virtualization. However, the
> sampling can not be supported as there is no mechanism to enabled
> trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot
> to provide the counter overflow
On Wed, Apr 03, 2024 at 01:04:41AM -0700, Atish Patra wrote:
> PMU Snapshot function allows to minimize the number of traps when the
> guest access configures/access the hpmcounters. If the snapshot feature
> is enabled, the hypervisor updates the shared memory with counter
> data and state of over
On Wed, Apr 03, 2024 at 12:36:41AM -0700, Atish Patra wrote:
> On 4/1/24 15:36, Atish Patra wrote:
> > On Sat, Mar 2, 2024 at 1:49 AM Andrew Jones wrote:
> > >
> > > On Wed, Feb 28, 2024 at 05:01:23PM -0800, Atish Patra wrote:
...
> > >
On Wed, Apr 03, 2024 at 01:04:40AM -0700, Atish Patra wrote:
> Currently, we return a linux error code if creating a perf event failed
> in kvm. That shouldn't be necessary as guest can continue to operate
> without perf profiling or profiling with firmware counters.
>
> Return appropriate SBI err
On Mon, Apr 01, 2024 at 03:37:01PM -0700, Atish Patra wrote:
> On Sat, Mar 2, 2024 at 12:16 AM Andrew Jones wrote:
> >
> > On Wed, Feb 28, 2024 at 05:01:22PM -0800, Atish Patra wrote:
> > > Currently, we return a linux error code if creating a perf event failed
> &g
On Wed, Apr 03, 2024 at 01:04:35AM -0700, Atish Patra wrote:
...
> +static int pmu_sbi_snapshot_disable(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, -1,
> + -1, 0, 0, 0, 0);
The "Rename the SBI_STA_SHMEM_DISABLE"
gt;
> - if (shmem_phys_lo == SBI_STA_SHMEM_DISABLE &&
> - shmem_phys_hi == SBI_STA_SHMEM_DISABLE) {
> + if (shmem_phys_lo == SBI_SHMEM_DISABLE &&
> + shmem_phys_hi == SBI_SHMEM_DISABLE) {
> vcpu->arch.sta.shmem = INVALID_GPA;
> return 0;
> }
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
sample_period = (-pmc->counter_val) & counter_val_mask;
>
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask;
> + /* Start all the counters that did not overflow in a single
> shot */
> + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i *
> BITS_PER_LONG, ctr_start_mask,
> + 0, 0, 0, 0);
> + }
>
> /* Reinitialize and start all the counter that overflowed */
> while (ctr_ovf_mask) {
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Wed, Apr 03, 2024 at 01:04:35AM -0700, Atish Patra wrote:
> SBI v2.0 SBI introduced PMU snapshot feature which adds the following
> features.
>
> 1. Read counter values directly from the shared memory instead of
> csr read.
> 2. Start multiple counters with initial values with one SBI call.
>
XT_DBCN_CONSOLE_WRITE = 0,
> @@ -285,6 +295,7 @@ struct sbi_sta_struct {
> #define SBI_ERR_ALREADY_AVAILABLE -6
> #define SBI_ERR_ALREADY_STARTED -7
> #define SBI_ERR_ALREADY_STOPPED -8
> +#define SBI_ERR_NO_SHMEM -9
>
> extern unsigned long sbi_spec_version;
> struct sbiret {
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
erf_event *event)
> cmask = 1;
> } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) {
> cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
> - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE);
> + cmask = BIT(CSR_INSTRET - CSR_CYCLE);
> }
> }
>
> --
> 2.34.1
>
Other than the commit message,
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Apr 03, 2024 at 01:04:32AM -0700, Atish Patra wrote:
> SBI v2.0 introduced a explicit function to read the upper 32 bits
> for any firmware counter width that is longer than 32bits.
> This is only applicable for RV32 where firmware counter can be
> 64 bit.
>
> Reviewe
/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid {
> SBI_EXT_PMU_COUNTER_START,
> SBI_EXT_PMU_COUNTER_STOP,
> SBI_EXT_PMU_COUNTER_FW_READ,
> + SBI_EXT_PMU_COUNTER_FW_READ_HI,
> };
>
> union sbi_pmu_ctr_info {
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
(CSR_SSCOUNTOVF),\
> + "csrr %0, " __stringify(CSR_SCOUNTOVF), \
> "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
> THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
> CONFIG_ERRATA_THEAD_PMU,\
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Mon, Apr 01, 2024 at 04:20:18PM +0800, Haibo Xu wrote:
> This is the first patch to enable the base extension selftest
> for the SBI implementation in KVM. Test for other extensions
> will be added later.
I'm not sure we want SBI tests in KVM selftests since we already
plan to add them to kvm-u
On Wed, Mar 27, 2024 at 05:42:54AM +, Manali Shukla wrote:
...
> diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h
> b/tools/testing/selftests/kvm/include/kvm_util_base.h
> index 4a40b332115d..00e37c376cf3 100644
> --- a/tools/testing/selftests/kvm/include/kvm_util_base.h
> +++
On Wed, Feb 28, 2024 at 05:01:30PM -0800, Atish Patra wrote:
> Add a test for verifying overflow interrupt. Currently, it relies on
> overflow support on cycle/instret events. This test works for cycle/
> instret events which support sampling via hpmcounters on the platform.
> There are no ISA exte
On Wed, Feb 28, 2024 at 05:01:29PM -0800, Atish Patra wrote:
> Verify PMU snapshot functionality by setting up the shared memory
> correctly and reading the counter values from the shared memory
> instead of the CSR.
>
> Signed-off-by: Atish Patra
> ---
> .../selftests/kvm/include/riscv/processo
On Wed, Feb 28, 2024 at 05:01:28PM -0800, Atish Patra wrote:
> This test implements basic sanity test and cycle/instret event
> counting tests.
>
> Signed-off-by: Atish Patra
> ---
> tools/testing/selftests/kvm/Makefile| 1 +
> tools/testing/selftests/kvm/riscv/sbi_pmu.c | 340
On Wed, Feb 28, 2024 at 05:01:27PM -0800, Atish Patra wrote:
> The SBI PMU extension definition is required for upcoming SBI PMU
> selftests.
>
> Signed-off-by: Atish Patra
> ---
> .../selftests/kvm/include/riscv/processor.h | 67 +++
> 1 file changed, 67 insertions(+)
>
> dif
ONFIG(svinval, SVINVAL);
> KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
> @@ -980,6 +983,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_fp_d,
> &config_h,
> &config_smstateen,
> + &config_sscofpmf,
> &config_sstc,
> &config_svinval,
> &config_svnapot,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Wed, Feb 28, 2024 at 05:01:25PM -0800, Atish Patra wrote:
> The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware
> counters for RV32 based systems.
>
> Add infrastructure to support that.
>
> Reviewed-by: Anup Patel
> Signed-off-by: Atish Patra
> ---
> arch/riscv/include/as
On Wed, Feb 28, 2024 at 05:01:24PM -0800, Atish Patra wrote:
> KVM enables perf for guest via counter virtualization. However, the
> sampling can not be supported as there is no mechanism to enabled
> trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot
> to provide the counter overflow
On Wed, Feb 28, 2024 at 05:01:23PM -0800, Atish Patra wrote:
> PMU Snapshot function allows to minimize the number of traps when the
> guest access configures/access the hpmcounters. If the snapshot feature
> is enabled, the hypervisor updates the shared memory with counter
> data and state of over
On Wed, Feb 28, 2024 at 05:01:22PM -0800, Atish Patra wrote:
> Currently, we return a linux error code if creating a perf event failed
> in kvm. That shouldn't be necessary as guest can continue to operate
> without perf profiling or profiling with firmware counters.
>
> Return appropriate SBI err
kvm_pmu_release_perf_event(pmc);
> - }
> } else {
> sbiret = SBI_ERR_INVALID_PARAM;
> }
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Wed, Feb 28, 2024 at 05:01:20PM -0800, Atish Patra wrote:
> SBI v2.0 SBI introduced PMU snapshot feature which adds the following
> features.
>
> 1. Read counter values directly from the shared memory instead of
> csr read.
> 2. Start multiple counters with initial values with one SBI call.
>
On Wed, Feb 28, 2024 at 05:01:19PM -0800, Atish Patra wrote:
> SBI PMU Snapshot function optimizes the number of traps to
> higher privilege mode by leveraging a shared memory between the S/VS-mode
> and the M/HS mode. Add the definitions for that extension and new error
> codes.
>
> Reviewed-by:
eturn 0;
> }
>
> + if (sbi_spec_version >= sbi_mk_version(2, 0))
> + sbi_v2_available = true;
> +
> ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
> "perf/riscv/pmu:starting",
> pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
> --
> 2.34.1
>
Either way,
Reviewed-by: Andrew Jones
);
> KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC);
> @@ -987,6 +990,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_svinval,
> &config_svnapot,
> &config_svpbmt,
> + &config_zacas,
> &config_zba,
> &config_zbb,
> &config_zbc,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
ISCV_ISA_EXT_SSTC:
> case KVM_RISCV_ISA_EXT_SVINVAL:
> case KVM_RISCV_ISA_EXT_SVNAPOT:
> + case KVM_RISCV_ISA_EXT_ZACAS:
> case KVM_RISCV_ISA_EXT_ZBA:
> case KVM_RISCV_ISA_EXT_ZBB:
> case KVM_RISCV_ISA_EXT_ZBC:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
);
> @@ -1010,6 +1013,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zksed,
> &config_zksh,
> &config_zkt,
> + &config_ztso,
> &config_zvbb,
> &config_zvbc,
> &config_zvfh,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
KVM_RISCV_ISA_EXT_ZKSED:
> case KVM_RISCV_ISA_EXT_ZKSH:
> case KVM_RISCV_ISA_EXT_ZKT:
> + case KVM_RISCV_ISA_EXT_ZTSO:
> case KVM_RISCV_ISA_EXT_ZVBB:
> case KVM_RISCV_ISA_EXT_ZVBC:
> case KVM_RISCV_ISA_EXT_ZVFH:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
func csr_funcs[] = {
> KVM_RISCV_VCPU_AIA_CSR_FUNCS
> KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS
> + { .base = CSR_SEED, .count = 1, .func = seed_csr_rmw },
> };
>
> /**
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
d(),
> RISCV_ISA_EXT_ZICBOZ))
> - csr_set(CSR_SENVCFG, ENVCFG_CBZE);
> + csr_set(CSR_ENVCFG, ENVCFG_CBZE);
> }
>
> #ifdef CONFIG_RISCV_ALTERNATIVE
> --
> 2.43.0
>
Reviewed-by: Andrew Jones
On Mon, Jan 22, 2024 at 05:58:32PM +0800, Haibo Xu wrote:
> Change signed type to unsigned in test_args struct which
> only make sense for unsigned value.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Haibo Xu
> ---
> tools/testing/selftests/kvm/aarch64/arch_timer.c |
On Wed, Jan 17, 2024 at 04:25:14PM +0800, Yunhui Cui wrote:
> When compiling with -O0, the following error will occur:
> cbo.c: In function 'cbo_insn':
> cbo.c:43:9: warning: 'asm' operand 1 probably does not match constraints
>43 | asm volatile(
> | ^~~
> cbo.c:43:9: warn
changed, 4 insertions(+)
>
Reviewed-by: Andrew Jones
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
Reviewed-by: Andrew Jones
t; 1 file changed, 8 insertions(+)
>
Reviewed-by: Andrew Jones
> arch/riscv/kvm/vcpu_onereg.c | 4
> 2 files changed, 6 insertions(+)
>
Reviewed-by: Andrew Jones
t; 1 file changed, 4 insertions(+)
>
Reviewed-by: Andrew Jones
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
Reviewed-by: Andrew Jones
t; 1 file changed, 8 insertions(+)
>
Reviewed-by: Andrew Jones
> arch/riscv/kvm/vcpu_onereg.c | 4
> 2 files changed, 6 insertions(+)
>
Reviewed-by: Andrew Jones
; Signed-off-by: Anup Patel
> ---
> .../selftests/kvm/riscv/get-reg-list.c| 40 +++
> 1 file changed, 40 insertions(+)
>
Reviewed-by: Andrew Jones
sh, and Zvkt.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/include/uapi/asm/kvm.h | 10 ++
> arch/riscv/kvm/vcpu_onereg.c | 20
> 2 files changed, 30 insertions(+)
>
Reviewed-by: Andrew Jones
-by: Anup Patel
> ---
> .../selftests/kvm/riscv/get-reg-list.c| 40 +++
> 1 file changed, 40 insertions(+)
Reviewed-by: Andrew Jones
On Thu, Dec 21, 2023 at 10:58:40AM +0800, Haibo Xu wrote:
> On Wed, Dec 20, 2023 at 9:58 PM Marc Zyngier wrote:
> >
> > On Wed, 20 Dec 2023 13:51:24 +,
> > Haibo Xu wrote:
> > >
> > > On Wed, Dec 20, 2023 at 5:00 PM Marc Zyngier wrote:
> > > >
> > > > On 2023-12-20 06:50, Haibo Xu wrote:
> >
V_ISA_EXT_ZIFENCEI:
> case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
> case KVM_RISCV_ISA_EXT_ZIHPM:
> + case KVM_RISCV_ISA_EXT_ZKND:
> + case KVM_RISCV_ISA_EXT_ZKNE:
> + case KVM_RISCV_ISA_EXT_ZKNH:
> + case KVM_RISCV_ISA_EXT_ZKR:
> + case KVM_RISCV_ISA_EXT_ZKSED:
> + case KVM_RISCV_ISA_EXT_ZKSH:
> + case KVM_RISCV_ISA_EXT_ZKT:
> return false;
> /* Extensions which can be disabled using Smstateen */
> case KVM_RISCV_ISA_EXT_SSAIA:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
ICBOM);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
> @@ -761,6 +764,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_svpbmt,
> &config_zba,
> &config_zbb,
> + &config_zbc,
> &config_zbs,
> &config_zicbom,
> &config_zicboz,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
KVM_RISCV_ISA_EXT_SVNAPOT:
> case KVM_RISCV_ISA_EXT_ZBA:
> case KVM_RISCV_ISA_EXT_ZBB:
> + case KVM_RISCV_ISA_EXT_ZBC:
> case KVM_RISCV_ISA_EXT_ZBS:
> case KVM_RISCV_ISA_EXT_ZICNTR:
> case KVM_RISCV_ISA_EXT_ZICOND:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
ension without any additional ONE_REG registers
> 2) KVM_ISA_EXT_SUBLIST_CONFIG - Macro to generate reg_list for
>ISA extension with additional ONE_REG registers
This patch also adds the missing config for svnapot.
Reviewed-by: Andrew Jones
Thanks,
drew
>
> Signed-off-by: Anup
On Thu, Nov 02, 2023 at 12:01:25PM +, Yong-Xuan Wang wrote:
> Update the get-reg-list test to test the Svadu Extension is available
> for guest OS.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++
> 1 file changed, 18 insertion
nr_iter);
> - GUEST_ASSERT_EQ(config_iter + 1, irq_iter);
> + __GUEST_ASSERT(config_iter + 1 == irq_iter,
> + "config_iter + 1 = 0x%lx, irq_iter = 0x%lx.\n"
> + " Guest timer interrupt was not trigged within the
> specified\n"
> + " interval, try to increase the error margin by [-e]
> option.\n",
> + config_iter + 1, irq_iter);
> }
> }
>
> --
> 2.34.1
>
I probably would have started the series with this patch since you said
you could reproduce the problem on aarch64. Starting the series with
this patch would allow just this patch to get picked up to fix aarch64,
if that's necessary, and also avoids touching a couple places twice
with the code split for riscv.
But anyway, other than the missing space in the help text,
Reviewed-by: Andrew Jones
Thanks,
drew
5 +-
> .../testing/selftests/kvm/riscv/arch_timer.c | 107 ++
> 7 files changed, 206 insertions(+), 10 deletions(-)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/arch_timer.h
> create mode 100644 tools/testing/selftests/kvm/riscv/arch_timer.c
>
Reviewed-by: Andrew Jones
On Tue, Dec 12, 2023 at 05:31:17PM +0800, Haibo Xu wrote:
> Add guest_get_vcpuid() helper to simplify accessing to per-cpu
> private data. The sscratch CSR was used to store the vcpu id.
>
> Signed-off-by: Haibo Xu
> Reviewed-by: Andrew Jones
> ---
> tools/testing/selftest
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