Hi Niklas,
On Tuesday, 11 December 2018 04:01:15 EET Niklas Söderlund wrote:
> On 2018-12-10 22:16:52 +0200, Laurent Pinchart wrote:
> > On Monday, 10 December 2018 16:53:55 EET Jacopo Mondi wrote:
> >> The PHTW selection algorithm implemented in rcsi2_phtw_write_mbps()
> >> checks for lower bound
Hi Sakari,
On Mon, Dec 10, 2018 at 9:22 PM Sakari Ailus
wrote:
>
> Address a few false positive compiler warnings related to uninitialised
> variables. While at it, use bool where bool is needed and %u to print an
> unsigned integer.
>
> Signed-off-by: Sakari Ailus
> ---
> drivers/staging/media
This message is generated daily by a cron job that builds media_tree for
the kernels and architectures in the list below.
Results of the daily build of media_tree:
date: Tue Dec 11 05:00:11 CET 2018
media-tree git hash:e159b6074c82fe31b79aad672e02fa204dbbc6d8
media_build git
Hi Laurent,
Thanks for your feedback,
On 2018-12-10 22:16:52 +0200, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Monday, 10 December 2018 16:53:55 EET Jacopo Mondi wrote:
> > The PHTW selection algorithm implemented in rcsi2_phtw_write_mbps() checks
> > for lower bou
Without this, cpumask_t and bool are not defined:
In file included from drivers/media/pci/ddbridge/ddbridge-ci.c:19:
In file included from drivers/media/pci/ddbridge/ddbridge.h:22:
./arch/arm/include/asm/irq.h:35:50: error: unknown type name 'cpumask_t'
extern void arch_trigger_cpumask_backtrace(c
On Mon, 10 Dec 2018 17:22:41 +0530, Jagan Teki wrote:
> Allwinner A64 CSI has single channel time-multiplexed BT.656
> CMOS sensor interface like H3 but work by lowering clock than
> default mod clock.
>
> Add a compatible string for it.
>
> Signed-off-by: Jagan Teki
> ---
> Documentation/devic
Document the bindings.
Signed-off-by: Eddie James
Reviewed-by: Rob Herring
---
.../devicetree/bindings/media/aspeed-video.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/aspeed-video.txt
diff --git a/Documentatio
The Video Engine (VE) embedded in the Aspeed AST2400 and AST2500 SOCs
can capture and compress video data from digital or analog sources. With
the Aspeed chip acting a service processor, the Video Engine can capture
the host processor graphics output.
Add a V4L2 driver to capture video data and co
From: Eddie James
The Video Engine (VE) embedded in the Aspeed AST2400 and AST2500 SOCs
can capture and compress video data from digital or analog sources. With
the Aspeed chip acting as a service processor, the Video Engine can
capture the host processor graphics output.
This series adds a V4L2
Hi Jacopo
Let's see what I have done
On Sun, Dec 9, 2018 at 8:39 PM jacopo mondi wrote:
>
> Hi Michael, Jagan, Hans,
>
> On Sat, Dec 08, 2018 at 06:07:04PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > Down you have my tentative of connection
> >
> > I need to hack a bit to have tuner
From: Yong Zhi
Add support for metadata output video nodes, in other words,
V4L2_CAP_META_OUTPUT and V4L2_BUF_TYPE_META_OUTPUT.
Signed-off-by: Sakari Ailus
Signed-off-by: Yong Zhi
Signed-off-by: Sakari Ailus
---
utils/common/v4l-helpers.h | 14 +-
utils/common/v4
This brings the META_OUTPUT buffer type as well as the related capability.
Signed-off-by: Sakari Ailus
---
include/linux/videodev2.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 9350bdc1..6aae99ea 100644
--- a/include/linux/vid
Hi all,
Here are the patches needed to support the META_OUTPUT queue type for
v4l2-compliance. The patch that adds the support is preceded by the kernel
header update --- the headers have been recently updated and there were
no other changes.
Sakari Ailus (1):
Update uAPI headers from the kerne
On Mon, Dec 10, 2018 at 11:08:43PM +0200, sakari.ai...@iki.fi wrote:
> Hi Mauro,
>
> Here's the ipu3 staging driver plus the META_OUTPUT buffer type needed to
> pass the parameters for the device. If you think this there's still time to
> get this to 4.20, then please pull. The non-staging patches
Hi Mauro,
Here's the ipu3 staging driver plus the META_OUTPUT buffer type needed to
pass the parameters for the device. If you think this there's still time to
get this to 4.20, then please pull. The non-staging patches have been
around for more than half a year and they're relatively simple.
I'l
Hi Yong, others,
On Thu, Dec 06, 2018 at 07:03:25PM -0600, Yong Zhi wrote:
> Hi,
>
> This series adds support for the Intel IPU3 (Image Processing Unit)
> ImgU which is essentially a modern memory-to-memory ISP. It implements
> raw Bayer to YUV image format conversion as well as a large number of
On Mon, Dec 10, 2018 at 06:07:10PM +0100, Hans Verkuil wrote:
> Hi Thierry,
>
> On 12/10/18 5:00 PM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > The CEC controller found on Tegra186 and Tegra194 is the same as on
> > earlier generations.
>
> Well... at least for the Tegra186 there is
All other drivers that need RC_CORE have a dependency rather than using
'select', so we should do the same here to avoid circular dependencies
as well as this warning about missing dependencies:
WARNING: unmet direct dependencies detected for RC_CORE
Depends on [n]: INPUT [=n]
Selected by [y]:
Hi Kieran,
Thank you for the patch.
On Friday, 7 December 2018 18:31:34 EET Kieran Bingham wrote:
> In the partition sizing the term 'prevents' is inappropriately
> pluralized. Simplify to 'prevent'.
>
> Signed-off-by: Kieran Bingham
Reviewed-by: Laurent Pinchart
and applied to my tree.
>
Hi Jacopo,
Thank you for the patch.
On Monday, 10 December 2018 16:53:55 EET Jacopo Mondi wrote:
> The PHTW selection algorithm implemented in rcsi2_phtw_write_mbps() checks
> for lower bound of the interval used to match the desired bandwidth. Use
> that in place of the currently used upport bou
From: Christoph Hellwig
Date: Mon, 10 Dec 2018 20:22:28 +0100
> On Mon, Dec 10, 2018 at 10:10:39AM -0800, David Miller wrote:
>> From: Christoph Hellwig
>> Date: Mon, 10 Dec 2018 17:32:56 +0100
>>
>> > Dave, can you pick the series up through the sparc tree? I could also
>> > merge it through
On Mon, Dec 10, 2018 at 07:19:30PM +, Robin Murphy wrote:
> On 08/12/2018 17:36, Christoph Hellwig wrote:
>> There is no need to have an additional kernel mapping for a contiguous
>> allocation if the device already is DMA coherent, so skip it.
>
> FWIW, the "need" was that it kept the code in
On Mon, Dec 10, 2018 at 10:10:39AM -0800, David Miller wrote:
> From: Christoph Hellwig
> Date: Mon, 10 Dec 2018 17:32:56 +0100
>
> > Dave, can you pick the series up through the sparc tree? I could also
> > merge it through the dma-mapping tree, but given that there is no
> > dependency on it t
On 08/12/2018 17:36, Christoph Hellwig wrote:
There is no need to have an additional kernel mapping for a contiguous
allocation if the device already is DMA coherent, so skip it.
FWIW, the "need" was that it kept the code in this path simple and the
mapping behaviour consistent with the regula
On Sat, Dec 08, 2018 at 07:52:04PM -0300, Ezequiel Garcia wrote:
> > #ifdef CONFIG_DMA_API_DEBUG
> > @@ -773,7 +791,7 @@ static void *__dma_alloc(struct device *dev, size_t
> > size, dma_addr_t *handle,
> >
> > if (cma)
> > buf->allocator = &cma_allocator;
> > - else if (is_co
From: Christoph Hellwig
Date: Mon, 10 Dec 2018 17:32:56 +0100
> Dave, can you pick the series up through the sparc tree? I could also
> merge it through the dma-mapping tree, but given that there is no
> dependency on it the sparc tree seem like the better fit.
I thought that some of this is a
On Sun, Dec 09, 2018 at 07:11:18AM +, French, Nicholas A. wrote:
> A typo in code cleanup commit db9c1007bc07 ("media: lgdt330x: do
> some cleanups at status logic") broke the FE_HAS_LOCK reporting
> for 3303 chips by inadvertently modifying the register mask.
>
> The broken lock status is cri
On 12/10/18 5:14 PM, Helen Koike wrote:
> Hi Hans,
>
> On 12/10/18 9:31 AM, Hans Verkuil wrote:
>> On 12/7/18 7:22 PM, Helen Koike wrote:
>
>>
>> The previewer is effectively similar to a debayer block.
>
> You mean the image it outputs?
Yes. It takes a bayer image and outputs a non-bayer fo
On 12/10/18 5:36 PM, Hans Verkuil wrote:
> On 12/10/18 5:34 PM, Thierry Reding wrote:
>> From: Thierry Reding
>>
>> Most of the CEC support code already lives in the "output" library code.
>> Move registration and unregistration to the library code as well to make
>> use of the same code with HDMI
Hi Thierry,
On 12/10/18 5:00 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> The CEC controller found on Tegra186 and Tegra194 is the same as on
> earlier generations.
Well... at least for the Tegra186 there is a problem that needs to be addressed
first.
No idea if this was solved for the
On 12/10/18 5:34 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> Most of the CEC support code already lives in the "output" library code.
> Move registration and unregistration to the library code as well to make
> use of the same code with HDMI on Tegra210 and later via the SOR.
>
> Signed
From: Thierry Reding
Most of the CEC support code already lives in the "output" library code.
Move registration and unregistration to the library code as well to make
use of the same code with HDMI on Tegra210 and later via the SOR.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/tegra/drm.h
Dave, can you pick the series up through the sparc tree? I could also
merge it through the dma-mapping tree, but given that there is no
dependency on it the sparc tree seem like the better fit.
Hi Hans,
On 12/10/18 9:31 AM, Hans Verkuil wrote:
> On 12/7/18 7:22 PM, Helen Koike wrote:
>> Add API to allow userspace to create any type of topology in vimc using
>> basic system calls such as mkdir/rmdir/read/write.
>>
>> Signed-off-by: Helen Koike
>>
>> ---
>> Hi,
>>
>> This patch introduces
From: Thierry Reding
Exporting the OF device ID match table allows udev to automatically load
the module upon receiving an "ADD" uevent for the CEC controller device.
Signed-off-by: Thierry Reding
---
drivers/media/platform/tegra-cec/tegra_cec.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
From: Thierry Reding
The CEC controller found on Tegra186 and Tegra194 is the same as on
earlier generations.
Signed-off-by: Thierry Reding
---
drivers/media/platform/tegra-cec/tegra_cec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/platform/tegra-cec/tegra_cec.c
b/dri
Hi Jacopo,
Thanks for fixing this.
On 2018-12-10 15:53:55 +0100, Jacopo Mondi wrote:
> The PHTW selection algorithm implemented in rcsi2_phtw_write_mbps() checks for
> lower bound of the interval used to match the desired bandwidth. Use that
> in place of the currently used upport bound.
>
> Fix
The PHTW selection algorithm implemented in rcsi2_phtw_write_mbps() checks for
lower bound of the interval used to match the desired bandwidth. Use that
in place of the currently used upport bound.
Fixes: 10c08812fe60 ("media: rcar: rcar-csi2: Update V3M/E3 PHTW tables")
Signed-off-by: Jacopo Mond
Hi Niklas,
On 10/12/2018 12:55, Niklas Söderlund wrote:
> Hi Koji-san, Kieran(-san),
>
> Thanks for your work.
>
> On 2018-12-10 12:29:01 +, Kieran Bingham wrote:
>> From: Koji Matsuoka
>>
>> The ADV7481 Register Control Manual states that bit 2 in the Video
>> Standard Selection register i
Add support for controls required by gstreamer V4L2 H265 encoder module:
* V4L2_CID_MPEG_VIDEO_HEVC_PROFILE
* V4L2_CID_MPEG_VIDEO_HEVC_LEVEL
Signed-off-by: Kelvin Lawson
---
drivers/media/platform/qcom/venus/venc_ctrls.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(
A quick status update regarding creating test scripts for regression
testing on kernelci.
I'm also CC-ing Dmitry to give an update on the work fixing syzkaller bugs.
On 11/6/18 9:37 AM, Hans Verkuil wrote:
> Hi all,
>
> After the media summit (heavy on test discussions) and the V4L2 event
> reg
Hi Koji-san, Kieran(-san),
Thanks for your work.
On 2018-12-10 12:29:01 +, Kieran Bingham wrote:
> From: Koji Matsuoka
>
> The ADV7481 Register Control Manual states that bit 2 in the Video
> Standard Selection register is reserved with the value of 1.
>
> The bit is otherwise undocumented
On 19.10.2018 15:52, Luis Oliveira wrote:
> Add the Synopsys MIPI CSI-2 controller driver. This
> controller driver is divided in platform dependent functions
> and core functions. It also includes a platform for future
> DesignWare drivers.
>
> Signed-off-by: Luis Oliveira
> ---
> Changelog
>
Hi Kieran,
Thank you for the patch.
On Monday, 10 December 2018 13:18:08 EET Kieran Bingham wrote:
> Provide a new option '--reset-controls' which will enumerate the
> available controls on a device or sub-device, and re-initialise them to
> defaults.
>
> Signed-off-by: Kieran Bingham
>
> ---
Hi,
On Mon, Dec 10, 2018 at 10:51:33AM +1100, David Howe wrote:
> hi
>
> using the experimental version of the media stack and i get this
>
> [ 80.606898] dvb-usb: found a 'DViCO FusionHDTV DVB-T NANO2 w/o firmware'
> in cold state, will try to load a firmware
> [ 80.620010] dvb-usb: downloa
Hi Matsuoka-san,
Thank you for the patch,
On 10/12/2018 12:07, Kieran Bingham wrote:
> From: Koji Matsuoka
>
> By video decoder user's manual, the bit 2 in Video Standard
> Selection register must be reserved with the value of 1.
> This driver cleared it with 0 when writing back.
> This patch c
Dne 09. 12. 18 v 23:04 Sakari Ailus napsal(a):
> Hi Petr,
>
> What's the status of this set? It would seem that addressing the issues
> is fairly trivial. Please also see a few comments below.
>
Hi,
Gonna work on it this week. I've had to work on higher priority stuff
last two months some of wh
From: Koji Matsuoka
The ADV7481 Register Control Manual states that bit 2 in the Video
Standard Selection register is reserved with the value of 1.
The bit is otherwise undocumented, and currently cleared by the driver
when setting the video standard selection.
Define the bit as reserved, and e
Address a few false positive compiler warnings related to uninitialised
variables. While at it, use bool where bool is needed and %u to print an
unsigned integer.
Signed-off-by: Sakari Ailus
---
drivers/staging/media/ipu3/ipu3.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
From: Koji Matsuoka
By video decoder user's manual, the bit 2 in Video Standard
Selection register must be reserved with the value of 1.
This driver cleared it with 0 when writing back.
This patch corrects it.
Signed-off-by: Koji Matsuoka
---
drivers/media/i2c/adv748x/adv748x-afe.c | 3 ++-
dr
On Fri, Dec 07, 2018 at 04:31:34PM +, Kieran Bingham wrote:
> In the partition sizing the term 'prevents' is inappropriately
> pluralized. Simplify to 'prevent'.
>
> Signed-off-by: Kieran Bingham
Reviewed-by: Simon Horman
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
So use separate compatibe to support it.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
1 file changed, 1 insert
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
Add a compatible string for it.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 +
1 file changed, 1 insertion(+)
This series support CSI on Allwinner A64.
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
Changes for v3:
- update dt-bindings for A64
- set mod clock via csi driver
- remove assign clocks from dtsi
- re
Some camera modules have the SoC feeding a master clock to the sensor
instead of having a standalone crystal. This clock signal is generated
from the clock control unit and output from the CSI MCLK function of
pin PE1.
Add a pinmux setting for it for camera sensors to reference.
Signed-off-by: Ja
Amarula A64-Relic board by default bound with OV5640 camera,
so add support for it with below pin information.
- PE13, PE12 via i2c-gpio bitbanging
- CLK_CSI_MCLK as external clock
- PE1 as external clock pin muxing
- ALDO1 as AVDD supply
- DLDO3 as DOVDD supply
- ELDO3 as DVDD supply
- PE14 gpio
Allwinner A64 CSI controller has similar features as like in
H3, but work by lowering clock than default mod clock.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/s
The default CSI_SCLK seems unable to drive the sensor to capture
the image, so update it to working clock rate 300MHz for A64.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/media/platform/sunxi/su
On 12/7/18 7:22 PM, Helen Koike wrote:
> Add API to allow userspace to create any type of topology in vimc using
> basic system calls such as mkdir/rmdir/read/write.
>
> Signed-off-by: Helen Koike
>
> ---
> Hi,
>
> This patch introduces the configufs API for configuring the topology in
> vimc w
Provide a new option '--reset-controls' which will enumerate the
available controls on a device or sub-device, and re-initialise them to
defaults.
Signed-off-by: Kieran Bingham
---
v2:
- Rebase and rework to sit on top of the compound control changes
With this patch, and the updated VSP-Tests
Hello,
On Monday, 10 December 2018 01:31:04 EET sakari.ai...@iki.fi wrote:
> Hi Edgar,
>
> Apologies for the late reply. I was going through the pending patches in
> Patchwork, and noticed this one.
>
> On Thu, Aug 23, 2018 at 08:56:50AM +0200, Edgar Thier wrote:
> > These formats are compressed
Hi,
On Fri, 2018-12-07 at 22:22 +0100, Jernej Škrabec wrote:
> Hi!
>
> Dne sreda, 05. december 2018 ob 10:24:44 CET je Paul Kocialkowski napisal(a):
> > This adds the Video Engine node for the A64. Since it can map the whole
> > DRAM range, there is no particular need for a reserved memory node
>
On Mon, Dec 10, 2018 at 08:59:02AM +0100, jacopo mondi wrote:
> Hi Sakari,
>thanks for digging this out
>
> On Mon, Dec 10, 2018 at 01:39:17AM +0200, sakari.ai...@iki.fi wrote:
> > Hi Jacopo,
> >
> > On Fri, Dec 29, 2017 at 01:22:26PM +0100, Jacopo Mondi wrote:
> > > The following commits:
> >
On Mon, Dec 10, 2018 at 08:59:36AM +0100, Hans Verkuil wrote:
> Wed works for me.
Same here.
--
Sakari Ailus
sakari.ai...@linux.intel.com
On Mon, Dec 10, 2018 at 4:57 PM Mauro Carvalho Chehab
wrote:
>
> Hi Tomasz,
>
> I mean Wed morning on my TZ, with would be Wed late afternoon on your TZ :-)
>
> As Hans pointed, we are at UTC-2 (Brazil), UTC+1 (Europe CET)
> and UTC+9 (Japan). Hans is proposing to have it 9am UTC.
>
> E, g:
>
>
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