Hi,
According to eMMC spec v4.3, Section 6.1 says that greater than 2GB
density cards are sector addressable and less than 2GB are byte addressable.
But Section 7.3.3 says that OCR bit 30 needs to be used which access mode
the host must use for all its future transactions.
In mainline kernel the
Linus,
Please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git for-linus
to fix a regression in resume-from-hibernate, and two minor driver bugs
on Atmel controllers. These have been tested in linux-next. Thanks.
The following changes since commit
Hi,
On Wed, Dec 22, 2010 at 10:20 PM, Mike Rapoport m...@compulab.co.il wrote:
Only one comment below, otherwise feel free to add
Acked-by: Mike Rapoport m...@compulab.co.il
Thanks!
+ if (gpio_is_valid(plat-wp_gpio)) {
+ rc = gpio_request(plat-wp_gpio, sdhci_wp);
+
This patch wires up LED debugging for the MMCIF boot
on the mackerel, which is all that is required to get MMCIF
boot functioning.
Cc: Magnus Damm magnus.d...@gmail.com
Cc: Kuninori Morimoto kuninori.morimoto...@renesas.com
Signed-off-by: Simon Horman ho...@verge.net.au
---
This patch depends on:
Hi Chris,
Can you include the s5pc210 external clock support? without this,
s5pc210 boards doesn't use the SDHCI.
I think Ben is busy with other task so can't reply your ack request.
To Ben,
Can you ack the s5pc210 patch?
Thank you,
Kyungmin Park
On Thu, Dec 23, 2010 at 5:56 PM, Chris Ball
This patch enables the interrupt generation for SDIO IRQs
of the sdhi controllers of the SoC. To make sure SDIO IRQs
are used, announce the MMC_CAP_SDIO_IRQ capability
on migor. Untested, therefore RFC.
Signed-off-by: Arnd Hannemann a...@arndnet.de
---
Changes since v2:
- Added missing include
This patch enables the interrupt generation for SDIO IRQs
of the sdhi controllers of the SoC. To make sure SDIO IRQs
are used announce the MMC_CAP_SDIO_IRQ capability
on ap325rxa. Untested, therefore RFC.
Signed-off-by: Arnd Hannemann a...@arndnet.de
---
arch/sh/boards/mach-ap325rxa/setup.c |
Changes since v2:
* Whitespace fixes
* Changed order of test in get_ro
What benefit has the reordering? (And just to make sure: You still
return -1 meaning read-only. I assume this is intentional)
--
Pengutronix e.K. | Wolfram Sang|
On Thu, Dec 23, 2010 at 03:27:54AM -0600, Olof Johansson wrote:
Some controllers misparse segment length 0 as being 0, not 65536. Add
a quirk to deal with it.
Signed-off-by: Olof Johansson o...@lixom.net
I tend to NACK it (but I am not the maintainer). I'd prefer to see a
draft of your idea
Philip Rakity prak...@marvell.com writes:
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
+#define APMU_SDH2APMU_REG(0x0e8)
+#define APMU_SDH3APMU_REG(0x0ec)
is this really correct? ARMADA 16x Application Processor Family
(October
On Thu, 23 Dec 2010, Ohad Ben-Cohen wrote:
On Sun, Dec 19, 2010 at 12:22 PM, Rafael J. Wysocki r...@sisk.pl wrote:
That said, I think we may do something different that perhaps will make your
life somewhat easier.
...
So, I think we can add a runtime only flag working as described above.
On Thu, Dec 23, 2010 at 3:26 AM, Wolfram Sang w.s...@pengutronix.de wrote:
On Thu, Dec 23, 2010 at 03:27:54AM -0600, Olof Johansson wrote:
Some controllers misparse segment length 0 as being 0, not 65536. Add
a quirk to deal with it.
Signed-off-by: Olof Johansson o...@lixom.net
I tend to
On Thu, Dec 23, 2010 at 3:23 AM, Wolfram Sang w.s...@pengutronix.de wrote:
Changes since v2:
* Whitespace fixes
* Changed order of test in get_ro
What benefit has the reordering? (And just to make sure: You still
return -1 meaning read-only. I assume this is intentional)\
Uh,
I am having trouble sending mails to this list. So just a test mail
please ignore.
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Hi Kyungmin,
On Thu, Dec 23, 2010 at 06:17:50PM +0900, Kyungmin Park wrote:
Can you include the s5pc210 external clock support?
As I said:
If Ben agrees, I'm happy to send it on.
If Ben stays silent, then I have to overrule him -- he's the maintainer
of this driver. I'm okay with doing that,
On Thu, Dec 09, 2010 at 07:16:53AM +0900, Simon Horman wrote:
This allows a ROM-able zImage to be written to MMC and
for SuperH Mobile ARM to boot directly from the MMCIF
hardware block.
This is achieved by the MaskROM loading the first portion
of the image into MERAM and then jumping to
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