Hi Philip,
-Original Message-
From: Philip Rakity [mailto:prak...@marvell.com]
Sent: Wednesday, March 09, 2011 11:04 AM
To: Nath, Arindam
Cc: c...@laptop.org; zhangfei@gmail.com; subha...@codeaurora.org;
linux-mmc@vger.kernel.org; Su, Henry; Lu, Aaron; anath@gmail.com
From: Ulf Hansson ulf.hans...@stericsson.com
When using mmc_try_claim_host the corresponding release
function is mmc_do_release_host, which then also must
be exported.
Reviewed-by: Jonas Aberg jonas.ab...@stericsson.com
Reviewed-by: Sebastian Rasmussen sebastian.rasmus...@stericsson.com
Hi all,
From the previous discussion, I do not think we have got a clear conclusion
about using maximum timeout value. At least we know from Jae hoon Chung
using 0xE for every case is not a good. So I want to suggest only use 0xE for
busy command. I personally preferred below
+1. Looks good to me from sd3.0 spec. prospective.
-Original Message-
From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
ow...@vger.kernel.org] On Behalf Of Arindam Nath
Sent: Friday, March 04, 2011 5:03 PM
To: c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com;
-Original Message-
From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
ow...@vger.kernel.org] On Behalf Of Arindam Nath
Sent: Friday, March 04, 2011 5:03 PM
To: c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com;
subha...@codeaurora.org;
On Fri, Mar 4, 2011 at 6:32 AM, Arindam Nath arindam.n...@amd.com wrote:
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about
Hi Subhash,
-Original Message-
From: subha...@codeaurora.org [mailto:subha...@codeaurora.org]
Sent: Wednesday, March 09, 2011 5:52 PM
To: Nath, Arindam; c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com; linux-
m...@vger.kernel.org; Su, Henry; Lu, Aaron;
Hi Subhash,
-Original Message-
From: subha...@codeaurora.org [mailto:subha...@codeaurora.org]
Sent: Wednesday, March 09, 2011 7:39 PM
To: Nath, Arindam; c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com; linux-
m...@vger.kernel.org; Su, Henry; Lu, Aaron;
Linus,
Please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git for-linus
for a final MMC regression fix against -rc1. Thanks.
The following changes since commit 214d93b02c4fe93638ad268613c9702a81ed9192:
Linus Torvalds (1):
Merge branch 'omap-fixes-for-linus' of
Hi Subhash,
-Original Message-
From: subha...@codeaurora.org [mailto:subha...@codeaurora.org]
Sent: Wednesday, March 09, 2011 11:35 PM
To: Nath, Arindam; c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com; linux-
m...@vger.kernel.org; Su, Henry; Lu, Aaron;
On Tue, Mar 8, 2011 at 3:39 PM, Grant Grundler grund...@google.com wrote:
Save and restore SDHCI interrupt mask during suspend/resume.
Enables ARM Tegra2 board to suspend/resume.
Signed-off-by: Venkat Rao v...@broadcom.com
Reviewed-by: Olof Johansson ol...@chromium.org
Reviewed-by: Grant
On Wed, Mar 9, 2011 at 12:24 PM, Andrei Warkentin andr...@motorola.com wrote:
On Tue, Mar 8, 2011 at 3:39 PM, Grant Grundler grund...@google.com wrote:
Save and restore SDHCI interrupt mask during suspend/resume.
Enables ARM Tegra2 board to suspend/resume.
Signed-off-by: Venkat Rao
On Wed, Mar 9, 2011 at 3:01 PM, Grant Grundler grund...@google.com wrote:
On Wed, Mar 9, 2011 at 12:24 PM, Andrei Warkentin andr...@motorola.com
wrote:
On Tue, Mar 8, 2011 at 3:39 PM, Grant Grundler grund...@google.com wrote:
Save and restore SDHCI interrupt mask during suspend/resume.
On Wed, Mar 9, 2011 at 3:10 PM, Andrei Warkentin andr...@motorola.com wrote:
On Wed, Mar 9, 2011 at 3:01 PM, Grant Grundler grund...@google.com wrote:
On Wed, Mar 9, 2011 at 12:24 PM, Andrei Warkentin andr...@motorola.com
wrote:
On Tue, Mar 8, 2011 at 3:39 PM, Grant Grundler
On Mar 4, 2011, at 3:32 AM, Arindam Nath wrote:
We decide on the current limit to be set for the card based on the
Capability of Host Controller to provide current at 1.8V signalling,
and the maximum current limit of the card as indicated by CMD6
mode 0. We then set the current limit for the
On Feb 15, 2011, at 1:35 AM, Arindam Nath wrote:
This patch adds support for setting UHS-I bus speed mode during UHS-I
initialization procedure. Since both the host and card can support
more than one bus speed, we select the highest speed based on both of
their capabilities. First we set the
On Wed, Mar 9, 2011 at 1:10 PM, Andrei Warkentin andr...@motorola.com wrote:
On Wed, Mar 9, 2011 at 3:01 PM, Grant Grundler grund...@google.com wrote:
On Wed, Mar 9, 2011 at 12:24 PM, Andrei Warkentin andr...@motorola.com
wrote:
On Tue, Mar 8, 2011 at 3:39 PM, Grant Grundler
On Wed, Mar 9, 2011 at 4:00 PM, Grant Grundler grund...@google.com wrote:
I see why above patch is necessary now.
I don't understand the relationship between the two. Can you
elaborate? Or point at docs?
I'd be happy to add comments to the code.
Ok, let me rephrase my original statement. I
Hi,
On Wed, Mar 9, 2011 at 3:11 PM, Andrei Warkentin andr...@motorola.com wrote:
Does kernel.org still need something to deal with state of
SDHCI_QUIRK_NO_SDIO_IRQ quirk bit?
I'm confused. I see this quirk added as part of Tegra sdhci support in
our K36 tree. I suppose with this patch the
On Wed, Mar 9, 2011 at 5:56 PM, Olof Johansson o...@lixom.net wrote:
Hi,
On Wed, Mar 9, 2011 at 3:11 PM, Andrei Warkentin andr...@motorola.com wrote:
Does kernel.org still need something to deal with state of
SDHCI_QUIRK_NO_SDIO_IRQ quirk bit?
I'm confused. I see this quirk added as part
I'm sending this as a new mail instead of a reply-to, because it's really a
different set of patches. I'm holding off on the reliability improvement,
because
the generic-code equiv. depends on reliable write support, so I'll wait until
everybody
is satisfied with these changes until sending
The current mechanism is SDIO-only.
Signed-off-by: Andrei Warkentin andr...@motorola.com
---
drivers/mmc/core/quirks.c | 130 ++---
1 files changed, 98 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/core/quirks.c b/drivers/mmc/core/quirks.c
This allows us to create quirks for block devices, without
creating messy Kconfig dependencies, or polluting core/ with
function-specific code.
Change-Id: I0fd466f115718a23edd0636e1e73d91c77b63887
Signed-off-by: Andrei Warkentin andr...@motorola.com
---
drivers/mmc/core/core.h |2 -
Block quirks implemented using core/quirks.c support.
Change-Id: I81d9ad57a7ae95c60ee8026f090c8df7c75fd069
Signed-off-by: Andrei Warkentin andr...@motorola.com
---
drivers/mmc/card/block.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/card/block.c
Adjust unaligned write accesses spanning preferred align
size into two accesses - an unaligned and an aligned access.
This is meant to be used for card quirks, and is off
by default. A limiting value in transfer size
for this adjustment is available, as on some cards there is a
perf decrease for
On Wed, Mar 9, 2011 at 6:54 PM, Andrei Warkentin andr...@motorola.com wrote:
I'm sending this as a new mail instead of a reply-to, because it's really a
different set of patches. I'm holding off on the reliability improvement,
because
the generic-code equiv. depends on reliable write support,
The current mechanism is SDIO-only.
Signed-off-by: Andrei Warkentin andr...@motorola.com
---
drivers/mmc/core/quirks.c | 142 +++--
1 files changed, 110 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/core/quirks.c b/drivers/mmc/core/quirks.c
On Wed, Mar 9, 2011 at 4:07 PM, Andrei Warkentin andr...@motorola.com wrote:
...
I believe Grant's change is necessary for any SDHCI controller with
SDIO and suspend/resume.
BTW, to pick nits, I'm not the author. Note the S-o-b lines in the
original patch:
Signed-off-by: Venkat Rao
Chuanxiao Dong wrote:
Hi all,
From the previous discussion, I do not think we have got a clear conclusion
about using maximum timeout value. At least we know from Jae hoon Chung
using 0xE for every case is not a good. So I want to suggest only use 0xE
for
busy command. I
Hi Philip,
-Original Message-
From: Philip Rakity [mailto:prak...@marvell.com]
Sent: Thursday, March 10, 2011 3:11 AM
To: Nath, Arindam
Cc: c...@laptop.org; zhangfei@gmail.com; subha...@codeaurora.org;
linux-mmc@vger.kernel.org; Su, Henry; Lu, Aaron; anath@gmail.com
Some cards have the CRC errors in read on mx51 BBG board.
Configure the eSDHC pad configurations to level up the
compatibility to fix this issue.
Signed-off-by: Richard Zhu hong-xing@freescale.com
Tested-by: Shawn Guo shawn@gmail.com
---
arch/arm/plat-mxc/include/mach/iomux-mx51.h | 40
-Original Message-
From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
ow...@vger.kernel.org] On Behalf Of subha...@codeaurora.org
Sent: Wednesday, March 09, 2011 4:15 PM
To: 'Arindam Nath'; c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com; linux-
On Thu, Mar 10, 2011 at 02:15:46PM +0800, Richard Zhu wrote:
Some cards have the CRC errors in read on mx51 BBG board.
Configure the eSDHC pad configurations to level up the
compatibility to fix this issue.
Signed-off-by: Richard Zhu hong-xing@freescale.com
Tested-by: Shawn Guo
-Original Message-
From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
ow...@vger.kernel.org] On Behalf Of Arindam Nath
Sent: Friday, March 04, 2011 5:03 PM
To: c...@laptop.org
Cc: zhangfei@gmail.com; prak...@marvell.com;
subha...@codeaurora.org;
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