Hi,
I am looking over the [RFC] mmcoops with panic/oops and is strikes
me that although platform data is used to limit the area of the MMC
device to which the oops is witten, the entire device has to belong
(be bound to) the mmc_oops driver and as such no part of the device
can be used for
Hi
Jaehoon Chung wrote:
Hi
Seungwon Jeon wrote:
Hi, Mr Chung.
Do you have any feedback?
I want to know how to manipulate clock for host or card on your test
situation.
Yes. i used clock for them.
I think there is no code for these clock in dw_mmc.
Who do you think is
This patch is added the quirk for Samsung SoCs.
Samsung SoCs need to set QUIRK_BROKEN_ADMA_ZEROLEN_DESC.
(If ADMA operation is more than 65535, maybe set by zero.)
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Hi Ido,
On Tue, Jul 12, 2011 at 02:33:11, Ido Yariv wrote:
Commit 7416401 (arm: davinci: Fix fallout from generic irq chip
conversion) introduced a bug, causing low level interrupt handlers to
get a bogus irq number as an argument. The gpio irq handler falsely
assumes that the handler data is
Calling mmc_request_done() under a spinlock with interrupts disabled
leads to a recursive spin-lock on request retry path and to
scheduling in atomic context. This patch fixes both these problems
by moving mmc_request_done() to the scheduler workqueue.
Signed-off-by: Guennadi Liakhovetski
On 12 July 2011 02:22, J Freyensee james_p_freyen...@linux.intel.com wrote:
On 07/10/2011 12:21 PM, Per Forlin wrote:
+MMC host extensions
+===
+
+There are two optional members in the
+mmc_host_ops -- pre_req() and post_req() -- that the host
+driver may implement in order
On 12 July 2011 06:23, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi
When I tested MMC card with IOzone, i found this message..
I tried to find what problem..but i didn't find yet..
So i want to get mailing's help..Have ever seen the below message?
(using SDHCI controller, eMMC 4.41 card,
Chris,
Test System: ThinkPad X220 Tablet, using Sandisk 2GB Class 2 SD, I did not
see any considerable change in read/write times. Also, tested a Transcend
MMCPlus 2GB card, before the patch was applied it would not mount the
card, and would cause IO errors on read/write, but after the patch
Hi Manoj,
On Tue, Jul 12 2011, Manoj Iyer wrote:
Test System: ThinkPad X220 Tablet, using Sandisk 2GB Class 2 SD, I did
not see any considerable change in read/write times. Also, tested a
Transcend MMCPlus 2GB card, before the patch was applied it would not
mount the card, and would cause IO
Chris,
btw only the 1st write was slower, subsequent writes looks ok.
=== before ===== after ==
real0m0.480s vs real0m0.757s
real0m0.476s vs real0m0.488s
real0m0.484s vs real0m0.484s
real0m0.480s vs real0m0.486s
I have attached the output of flashbench
Hi,
On Tue, Jul 12 2011, Manoj Iyer wrote:
btw only the 1st write was slower, subsequent writes looks ok.
[..]
I have attached the output of flashbench and the time test to
http://launchpad.net/bugs/773524
[..]
== Finding the number of open erase blocks ==
u@u:~/flash/flashbench$ sudo
On Tuesday 12 July 2011 19:30:42 Chris Ball wrote:
On Tue, Jul 12 2011, Manoj Iyer wrote:
btw only the 1st write was slower, subsequent writes looks ok.
[..]
I have attached the output of flashbench and the time test to
http://launchpad.net/bugs/773524
[..]
== Finding the number of
Hi Sekhar,
On Tue, Jul 12, 2011 at 02:52:17PM +0530, Nori, Sekhar wrote:
- g = (__force struct davinci_gpio_regs __iomem *)
irq_desc_get_handler_data(desc);
+ ctl = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
+ g = (struct davinci_gpio_regs __iomem
Hi Per.
#iozone -az -i 0 -i 1 -i 2 -s 200m -U /mnt/mmc -f /mnt/mmc/test -e
/mnt/mmc is mounted /dev/mmcblk0p6 for EXT4 filesystem.
It's my command..i tested with both SDHCI and DW_MMC controller.
DW_MMC controller didn't find that error message.
But SDHCI controller always occurred that error.
Hi,
I don't know meaning of QUIRK_BROKEN_ADMA_ZEROLEN_DESC exactly.
Is there any problem in ADMA descriptors?
Could you explain for this?
The following table is for ADMA length field from Host controller spec.
The maximum data length descriptor line is less than 64KiB.
Samsung also conforms
One use for this is as follows:
Without the QUIRK
imagine there is one SG descriptor passed in and it is properly aligned etc.
The prepare_data function (and friends) will
change this to 2 ADMA descriptors. The first descriptor will point to the data
/ length passed in via the SG
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