Although the HC supports HS200 (eMMC) the caps2 are always zero; this means that
no way to use the super speed mode (when init the card).
If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and
this patch just sets the MMC_CAP2_HS200 in the host caps2 field.
v2: Since SDR104 a
On 06/11/2013 07:28 PM, dingu...@altera.com wrote:
> From: Dinh Nguyen
>
> Add bindings for SD/MMC for SOCFPGA.
> Add "syscon" to the "altr,sys-mgr" binding.
Not sure how I see syscon is related to SD? That is a pretty vague name
as well.
> Signed-off-by: Dinh Nguyen
> Reviewed-by: Pavel Mache
Looks good to me.
But this patch has a dependency on '[PATCH 2/2] mmc: dw_mmc: Add support DW
SD/MMC driver on SOCFPGA'
After that, it can be applied.(SDMMC_CMD_USE_HOLD_REG should be moved in
dw_mmc.h)
Acked-by: Seungwon Jeon
Thanks,
Seungwon Jeon
On 06/11/13 2013 8:31 PM Heiko Stübner wrote
On Tue, Jun 11, 2013 at 07:08:16PM -0500, Dinh Nguyen wrote:
> Hi Olof,
>
> On Tue, 2013-06-11 at 16:27 -0700, Olof Johansson wrote:
> > Hi,
> >
> > On Wed, Jun 05, 2013 at 10:02:58AM -0500, dingu...@altera.com wrote:
> > > From: Dinh Nguyen
> > >
> > > Add platform specific functionality for t
On 06/11/13 2013 8:30 PM Heiko Stübner wrote:
> In a subsquent patch probe will need to do some handling of data from
> the dt match table. So to prevent the need for forward declarations,
> move probe and remove below the match table.
>
> Signed-off-by: Heiko Stuebner
Acked-by: Seungwon Jeon
On 06/12/13 9:29 AM Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.
>
> Signed-off-by: Dinh Nguyen
> Reviewed-by: Pavel Machek
> Acked-by: Ja
From: Dinh Nguyen
Add bindings for SD/MMC for SOCFPGA.
Add "syscon" to the "altr,sys-mgr" binding.
Signed-off-by: Dinh Nguyen
Reviewed-by: Pavel Machek
CC: Arnd Bergmann
CC: Olof Johansson
Cc: Pavel Machek
Cc: Grant Likely
Cc: Rob Herring
Cc: Chris Ball
Cc: devicetree-disc...@lists.ozlab
From: Dinh Nguyen
Add platform specific functionality for the DW SD/MMC driver for
SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
can use this define.
Signed-off-by: Dinh Nguyen
Reviewed-by: Pavel Machek
Acked-by: Jaehoon Chung
Acked-by: Olof Johansson
CC: Seungwon Jeon
From: Dinh Nguyen
Hi Chris,
I apologize for not including you in the original patch series. Can you can
review
and apply to your tree if there are not comments?
PATCH[1/2] - Bindings and documentation for dw_mmc-socfpga
PATCH[2/2] - SOCFPGA platform specific implementation for dw_mmc driver.
Hi Olof,
On Tue, 2013-06-11 at 16:27 -0700, Olof Johansson wrote:
> Hi,
>
> On Wed, Jun 05, 2013 at 10:02:58AM -0500, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add platform specific functionality for the DW SD/MMC driver for
> > SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so
I get the following lockdump output on p2020rdb using
v3.10-rc5-43-g34376a5. While it's not particularly polite for the
esdhc driver to be calling OF functions while holding another lock which
can be acquired from interrupt context, why is devtree_lock usually
acquired in an irqsafe manner but som
Hi,
On Wed, Jun 05, 2013 at 10:02:58AM -0500, dingu...@altera.com wrote:
> From: Dinh Nguyen
>
> Add platform specific functionality for the DW SD/MMC driver for
> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
> can use this define.
>
> Signed-off-by: Dinh Nguyen
> CC: Se
On 13-06-03 03:02 PM, Arnd Bergmann wrote:
Patch "mmc: sdhci: Add size for caller in init+register" changed the
interface for sdhci_pltfm_init, while patch "mmc: sdhci-sirf: add mmc
host sdhci-pltfm based driver for SiRF SoCs" added a new driver
with the old interface.
This changes the sirf driv
Quoting Heiko Stübner (2013-06-11 04:31:31)
> This adds basic support for clocks on Rockchip rk3066 SoCs.
> The clock handling thru small dt nodes is heavily inspired by the
> sunxi clk code.
>
> The plls are currently read-only, as their setting needs more
> investigation. This also results in sl
Am Dienstag, 11. Juni 2013, 20:57:50 schrieb Mike Turquette:
> Quoting Heiko Stübner (2013-06-11 04:29:32)
>
> > SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
> > that use the regular mechanisms for storage but allow only even
> > dividers and 1 to be used.
> >
> > Therefore a
Quoting Heiko Stübner (2013-06-11 04:29:32)
> SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
> that use the regular mechanisms for storage but allow only even
> dividers and 1 to be used.
>
> Therefore add a flag that lets _is_valid_div limit the valid dividers
> to these values
On Jun 11, 2013, at 3:09 PM, Giuseppe CAVALLARO wrote:
> Although the HC supports HS200 (eMMC) the caps2 are always zero; this means
> that
> no way to use the super speed mode (when init the card).
>
> If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and
> this patch ju
Although the HC supports HS200 (eMMC) the caps2 are always zero; this means that
no way to use the super speed mode (when init the card).
If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and
this patch just sets the MMC_CAP2_HS200 in the host caps2 field.
Reported-by: Youss
On Tue, Jun 11, 2013 at 3:37 PM, Andy Shevchenko
wrote:
> On Tue, Jun 11, 2013 at 3:06 PM, Heiko Stübner wrote:
>> Am Dienstag, 11. Juni 2013, 13:51:56 schrieb Andy Shevchenko:
>>> On Tue, Jun 11, 2013 at 2:29 PM, Heiko Stübner wrote:
> This variant I think fits:
>
> if (!(divider->flags & CLK_
On Tue, Jun 11, 2013 at 3:06 PM, Heiko Stübner wrote:
> Am Dienstag, 11. Juni 2013, 13:51:56 schrieb Andy Shevchenko:
>> On Tue, Jun 11, 2013 at 2:29 PM, Heiko Stübner wrote:
[]
>> > @@ -141,6 +149,8 @@ static bool _is_valid_div(struct clk_divider
>> > *divider, unsigned int div)
>> >
>> >
Am Dienstag, 11. Juni 2013, 13:51:56 schrieb Andy Shevchenko:
> On Tue, Jun 11, 2013 at 2:29 PM, Heiko Stübner wrote:
> > SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
> > that use the regular mechanisms for storage but allow only even
> > dividers and 1 to be used.
> >
> > Th
On Tue, Jun 11, 2013 at 2:29 PM, Heiko Stübner wrote:
> SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
> that use the regular mechanisms for storage but allow only even
> dividers and 1 to be used.
>
> Therefore add a flag that lets _is_valid_div limit the valid dividers
> to th
This adds basic support for clocks on Rockchip rk3066 SoCs.
The clock handling thru small dt nodes is heavily inspired by the
sunxi clk code.
The plls are currently read-only, as their setting needs more
investigation. This also results in slow cpu speeds, as the apll starts
at a default of 600mhz
This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: Heiko Stuebner
---
arc
Uarts on all recent Rockchip SoCs are Synopsis DesignWare 8250 types.
Only their addresses vary very much.
This patch adds the necessary definitions to use any of the uart ports
for early debug purposes.
Signed-off-by: Heiko Stuebner
---
arch/arm/Kconfig.debug| 34
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other modifications (additional register etc)
present, so to keep the footprint low, add this small variant to the
pltf
In a subsquent patch probe will need to do some handling of data from
the dt match table. So to prevent the need for forward declarations,
move probe and remove below the match table.
Signed-off-by: Heiko Stuebner
---
drivers/mmc/host/dw_mmc-pltfm.c | 28 ++--
1 files c
dw_mci_pltfm_remove gets exported and used by dw_mmc-exynos, so should
not be static.
Signed-off-by: Heiko Stuebner
Acked-by: Jaehoon Chung
Acked-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-pltfm.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mmc/host/dw_
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used.
Therefore add a flag that lets _is_valid_div limit the valid dividers
to these values. _get_maxdiv is also adapted to return even values
for
Third version of basic Rockchip A9 support.
The biggest change is probably the missing pinctrl driver which already found
its way into the pinctrl tree from Linus Walleij as part of the pinconfig
generalisation and should find its way into the mainline kernel from there.
But startup of rk3066-base
On Mon, Jun 10, 2013 at 5:03 PM, Ulf Hansson wrote:
> From: Ulf Hansson
>
> The MMC/SD/SDIO cards are registered on the mmc_bus and should from a power
> management perspective be controlled from there. As of today each and every
> host driver needs to issue mmc_suspend|resume_host from their re
On Mon, Jun 10, 2013 at 6:23 PM, Tony Lindgren wrote:
> We only should remux the pins that need remuxing as that's done
> every time hitting idle. So I think we should have the following
> default groups:
>
> default Static pins that don't change, no need to remux
> config
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