Hi!
1 Actual Use-Case
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I have a SDIO card with a Marvell 8787, that works fine on an i.MX53
with the drivers/net/wireless/mwifiex/sdio.c driver. On an i.MX35
however the loading of the firmware errors out on the very first
single-block transfer with 1024 bytes payload.
Dear, Alim,
Well, I'm not sure that this patch is correct.
But as you mentioned, we need to decide how control the HLE.
I will check the HLE on this weekend. Thanks for your effort.
Best Regards,
Jaehoon Chung
On 11/12/2013 01:12 PM, Alim Akhtar wrote:
Hi Seungwon/ Jaehoon,
I can see there
On Fri, November 15, 2013, Jaehoon Chung wrote:
Dear, Alim,
Well, I'm not sure that this patch is correct.
But as you mentioned, we need to decide how control the HLE.
I will check the HLE on this weekend. Thanks for your effort.
Thank you for remind.
HLE should be cleared at least
This patch set tries to deal with a minor irq issue seen on Marvell
Kirkwood SoCs with irqchip/irq-orion and mvsdio drivers. In contrast
to non-DT irq handling, irqchip driver does handle irqs a little bit
different. First of all, it reads irq cause register once and works
through all bits set
SDIO controllers found on Marvell Kirkwood SoCs seem to cause a late,
spurious irq although all interrupts have been disabled. This irq
doesn't do any harm, neither to HW nor driver. To avoid some
unexpected irq warning later, we workaround above issue by bailing
out of irq handler early, if we
mvsdio reports method of card detection with dev_notice, while for
removable cards it may be sane, for non-removable cards it is not.
Also, as the user cannot do anything about it, silence the message
by reducing it from dev_notice to dev_dbg.
Signed-off-by: Sebastian Hesselbarth
Hi,
On 09/19/2013 11:41 PM, Russell King wrote:
Replace the following sequence:
dma_set_mask(dev, mask);
dma_set_coherent_mask(dev, mask);
with a call to the new helper dma_set_mask_and_coherent().
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
---
From: Stephen Hurd sh...@broadcom.com
Add two new quirks needed by BCM57785 card reader:
SDHCI_QUIRK2_BROKEN_UHS:
Disables all UHS modes.
SDHCI_QUIRK2_BCM57785_CR:
Bit twiddles some Broadcom-specific registers and supresses an error
about the 64k bar0.
Add sdhci_pci_fixes for:
o the
From: Victor Kamensky victor.kamen...@linaro.org
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed
Hi,
On Fri, Nov 15, 2013 at 03:56:22PM -0800, Grant Grundler wrote:
From: Stephen Hurd sh...@broadcom.com
Add two new quirks needed by BCM57785 card reader:
SDHCI_QUIRK2_BROKEN_UHS:
Disables all UHS modes.
This seems appropriate. You _could_ use SDHCI_QUIRK_MISSING_CAPS and
hardcode
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