[PATCHv3 3/3] mmc: dw_mmc-exynos: Remove Exynos' custom prepare_command function

2013-12-08 Thread dinguyen
From: Dinh Nguyen The Exynos prepare_command function is only checking when to set the SDMMC_CMD_USE_HOLD_REG bit. Now that there is a generic way to check on when to set SDMMC_CMD_USE_HOLD_REG bit. Signed-off-by: Dinh Nguyen --- v3: none v2: none --- drivers/mmc/host/dw_mmc-exynos.c | 14 --

[PATCHv3 2/3] mmc: dw_mmc-pltm: Remove Rockchip's custom dw_mmc driver structure

2013-12-08 Thread dinguyen
From: Dinh Nguyen Rockchip's implementation of the dw_mmc controller only requires the setting of the SDMMC_CMD_USE_HOLD_REG on every command. With the patch to set the SDMMC_CMD_USE_HOLD_REG by checking the slot's speed mode, this Rockchip custom driver structure is no longer necessary. Signed-

[PATCHv3 1/3] mmc: dw_mmc: Enable the hold reg for certain speed modes

2013-12-08 Thread dinguyen
From: Dinh Nguyen This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200. According to the Synopsys databook :"To meet the relatively high Input Hold Time requirement for SDR12, SDR25, and other MMC speed

[PATCHv3 0/3] mmc: dw_mmc: Make the use of the hold reg generic

2013-12-08 Thread dinguyen
From: Dinh Nguyen Hi, This is v3 of the patch series that makes the setting of the SDMMC_CMD_USE_HOLD_REG bit generic. v3 differences: * Read the IHR(Implement HOLD Register) bit in the HCON register. Will not use the SDMMC_CMD_USE_HOLD_REG if the IHR bit is 0 and cclk_in_drv = 0. * Changes

Re: [PATCHv2 1/3] mmc: dw_mmc: Enable the hold reg for certain speed modes

2013-12-08 Thread Dinh Nguyen
Hi Jaehoon, On 12/8/13 7:24 PM, Jaehoon Chung wrote: > Hi Dinh, > > I known there is IMPLEMENT_HOLD_REG[22] at HCON register. > It didn't affect with this register? The current dw_mmc code does not do any check for this bit in the HCON register. But I'll add the check in v3: Dinh > > Best Regards

Re: [PATCHv2 3/3] mmc: dw_mmc-exynos: Remove Exynos' custom prepare_command function

2013-12-08 Thread Dinh Nguyen
Hi Arnd, On 12/6/13 10:12 PM, Arnd Bergmann wrote: > On Saturday 07 December 2013, dingu...@altera.com wrote: >> -static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr) >> -{ >> - /* >> -* Exynos4412 and Exynos5250 extends the use of CMD register with the >> -

Re: [PATCHv2 1/3] mmc: dw_mmc: Enable the hold reg for certain speed modes

2013-12-08 Thread Jaehoon Chung
Hi Dinh, I known there is IMPLEMENT_HOLD_REG[22] at HCON register. It didn't affect with this register? Best Regards, Jaehoon Chung On 12/07/2013 12:20 PM, dingu...@altera.com wrote: > From: Dinh Nguyen > > This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is > operating all