Hi Chris, Simon
Now, our new board would like to use sh_mobile_sdhi driver,
then, it is expecting sh_mobile_sdhi use regulator.
But, this regulator is based on GPIO driver,
and GPIO driver probe timing is after sh_mobile_sdhi.
So, sh_mobile_sdhi (= tmio_mmc_pio) use default ocr_avail,
Am Mittwoch, 11. Dezember 2013, 06:51:39 schrieb Beomho Seo:
This patch use mmc_gpio_request_cd function.
Signed-off-by: Beomho Seo beomho@samsung.com
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 56
+++---
From: Mark Brown broo...@linaro.org
It is possible that we may fail to set the clock rate, if we do so then
log the failure and don't bother reprogramming the IP.
Signed-off-by: Mark Brown broo...@linaro.org
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 8
Dear Arnd
On 12/12/2013 04:12 AM, Arnd Bergmann wrote:
On Wednesday 11 December 2013, zhangfei wrote:
I have not seen clk-table and clk-table-num before. Are these standard
properties? What are the units that are used here, what does the index mean?
clk-table and clk-table-num are private
Add dw_mmc-k3.c for k3v2, support sd/emmc
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Signed-off-by: Zhigang Wang brooke.wangzhig...@huawei.com
---
.../devicetree/bindings/mmc/k3-dw-mshc.txt | 59 +
drivers/mmc/host/Kconfig | 10 ++
fix mmc mailing list address error
On Thu, Dec 12, 2013 at 03:31:50PM +0100, Ludovic Desroches wrote:
Hi,
With v3.13-rc3 I have an error when the atmel-mci driver calls
flush_dcache_page (log at the end of the message).
Since I didn't have it before, I did a git bisect and the commit
On Wednesday 11 December 2013 04:12 AM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131210 02:17]:
Add pbias regulator node as a child of system control
module - syscon.
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 14 ++
On Wednesday 11 December 2013 12:03 AM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131210 06:36]:
pbias register controls internal power supply to sd card i/o pads
in most OMAPs (OMAP2-5, DRA7).
Control bits for selecting voltage level and
enabling/disabling are in the same PBIAS
On Thursday 12 December 2013, zhangfei wrote:
On 12/12/2013 04:12 AM, Arnd Bergmann wrote:
On Wednesday 11 December 2013, zhangfei wrote:
But aren't the times fixed for each mode? Why do you need to specify them in
the DT? I would expect that the clock rates for each mode are set in the
From: Dinh Nguyen dingu...@altera.com
Add a altr,socfpga-sdmmc-sdr-clk clock type in the SOCFPGA clock driver. This
clock type is not really a clock for say, but a mechanism to set the phase
shift of the clock that is used to feed the SD/MMC CIU's clock. This clock does
not have parent so it is
From: Dinh Nguyen dingu...@altera.com
Adds a new binding, altr,socfpga-sdmmc-sdr-clk. This is a new clock
binding that the SD/MMC driver can use the common clock framework to
set the appropriate clock phase shift settings for the CIU clock.
Also add the syscon binding to the altr,sys-mgr node.
From: Dinh Nguyen dingu...@altera.com
All implementations of the Synopsys DW SD/MMC IP have settings to control
the phase shift of the CIU clk. These phase shift settings are necessary for
the SD/MMC to correctly clock the card. All variants of the dw_mmc will need
these settings, but how they
From: Dinh Nguyen dingu...@altera.com
Enables the dw_mmc driver for SOCFPGA.
Signed-off-by: Dinh Nguyen dingu...@altera.com
---
v6: none
v5: Add dw_mmc driver into socfpga_defconfig
v4: none
v3: none
v2: none
---
arch/arm/configs/socfpga_defconfig |2 ++
1 file changed, 2 insertions(+)
From: Dinh Nguyen dingu...@altera.com
Hi,
This is v6 of the patch series to enable SD/MMC on the SOCFPGA platform.
V6 differences from V5:
* Adds a new patch to the series.
[mmc: dw_mmc: Add support to set the SDR and DDR timing through clock
framework]
This patch enables the setting for
From: Dinh Nguyen dingu...@altera.com
It turns now that the only really platform specific code that is needed for
SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
Since the Rockchip already has this functionality, re-use the code that is
already in dw_mmc-pltfm.c.
On 12/10/13 12:15 PM, Arnd Bergmann wrote:
On Tuesday 10 December 2013, Dinh Nguyen wrote:
On 12/5/13 2:57 PM, Arnd Bergmann wrote:
And in now way should the clock provider code look into the DT properties
of the
clock consumer. From what I can tell, the dw-mshc code already interprets
On Thu, Dec 12, 2013 at 12:26:42AM -0800, Kuninori Morimoto wrote:
Hi Chris, Simon
Now, our new board would like to use sh_mobile_sdhi driver,
then, it is expecting sh_mobile_sdhi use regulator.
But, this regulator is based on GPIO driver,
and GPIO driver probe timing is after
From: Mike Frysinger vap...@chromium.org
Fix the recurisve make targets by using $(MAKE). Otherwise we get lots of
warnings and issues with parallel builds.
Fix the install target -- the man subdir was missing a dummy target.
Add proper .PHONY markings.
Signed-off-by: Mike Frysinger
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
README | 12
1 file changed, 12 insertions(+)
create mode 100644 README
diff --git a/README b/README
new file mode 100644
index 000..e7d5210
--- /dev/null
+++ b/README
@@ -0,0 +1,12 @@
+Userspace tools for MMC/SD devices
+
On Thu, Dec 12, 2013 at 03:36:19PM +0100, Ludovic Desroches wrote:
fix mmc mailing list address error
On Thu, Dec 12, 2013 at 03:31:50PM +0100, Ludovic Desroches wrote:
Hi,
With v3.13-rc3 I have an error when the atmel-mci driver calls
flush_dcache_page (log at the end of the
Non-dts implementation supply required DMA channel numbers as
IORESOURCE_DMA. However, there is was no way to get them from
device tree.
Signed-off-by: Sergei Ianovich ynv...@gmail.com
CC: Daniel Mack zon...@gmail.com
CC: Arnd Bergmann a...@arndb.de
---
v1..v2
* add binding for next-gen dma
On 12/13/2013 04:40 AM, Arnd Bergmann wrote:
On Thursday 12 December 2013, zhangfei wrote:
On 12/12/2013 04:12 AM, Arnd Bergmann wrote:
On Wednesday 11 December 2013, zhangfei wrote:
But aren't the times fixed for each mode? Why do you need to specify them in
the DT? I would expect that the
On Tue, Dec 10, 2013 at 12:26 PM, Tim Kryger tim.kry...@linaro.org wrote:
On Mon, Dec 9, 2013 at 11:18 PM, Christian Daudt b...@fixthebug.org wrote:
Applied to armsoc/for-3.14/dt
Could you wait till other maintainers provide their acks and then take
the entire series into a branch that feeds
On Thu, Dec 5, 2013 at 11:20 AM, Tim Kryger tim.kry...@linaro.org wrote:
The frequency property in snps,dw-apb-uart entries are no longer
required if the rate of the external clock can be determined using the
clk api (see e302cd9 serial: 8250_dw: add support for clk api).
This patch replaces
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