Current implementation of sdhci_s3c_consider_clock() is highly
inefficient due to multiple integer divisions by variable performed in a
loop. Since only divisors that are powers of two are considered, this
patch replaces them with respective shifts, removing all the integer
divisions.
To fix scheduling while atomic happening in sdhci_s3c_set_clock() caused
by calling clk_get_rate() that might sleep, this patch modifies the
driver to cache rates of all bus clocks at probe time and then only use
those cache values.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
On platforms prior to Exynos the SDHCI block used internal clock
divider controlled by SELFREQ field of CLKCON register to divide base
clock selected from several external clocks fed to the block by
SELBASECLK bitfield of CONTROL2 register. Depending on wanted clock
frequency, different external
IS_ERR() must be used to make sure that not a valid clock was returned
by clk_get() and company.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/mmc/host/sdhci-s3c.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c
This patch modifies sdhci_s3c_consider_clock() to fail if bus clock
being considered can not provide frequency lower or equal requested,
instead of returning the lowest supported.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
drivers/mmc/host/sdhci-s3c.c | 9 -
1 file changed, 8
This patch reimplements functions calculating minimum and maximum clock
rates to leverage clock rate cache introduced by previous patches.
In addition, the calculation is simplified to just comparing input
clock rates (max case) or input clock rates divided by maximum divisor
(min case), which is
Currently the driver assumes at probe that controller is configured for
last valid enumerated bus clock. This assumption is completely wrong, as
there is no way to ensure such configuration until the hardware gets
first configured (by calling sdhci_s3c_set_clock()).
This patch modifies the driver
