From: Roger Tseng rogera...@realtek.com
This patchset adds modules to support Realtek USB vendor specific class flash
card reader: one base module in MFD subsystem and two host modules in both mmc
and memstick subsystems. The architecture is similar to rtsx_pci.
This work is done primarily to
From: Roger Tseng rogera...@realtek.com
Explain why there is no need to have a symmetric LED turn-on in resume handler
while calling rtsx_usb_turn_off_led() in suspend handler.
Signed-off-by: Roger Tseng rogera...@realtek.com
---
drivers/mfd/rtsx_usb.c | 6 ++
1 file changed, 6
From: Roger Tseng rogera...@realtek.com
Realtek USB memstick host driver provides memstick host support based on the
Realtek USB card reader MFD driver.
Signed-off-by: Roger Tseng rogera...@realtek.com
---
drivers/memstick/host/Kconfig | 10 +
drivers/memstick/host/Makefile | 1 +
On 10/04/14 23:27, Jörg Krause wrote:
On 02/13/14 10:28, Chen-Yu Tsai wrote:
Hi,
On Thu, Feb 13, 2014 at 5:13 PM, Tomasz Figalt;tomasz.figa@gt; wrote:
Hi Arend,
On 10.02.2014 20:17, Arend van Spriel wrote:
[...]
Hi Chen-Yu,
picking up this thread.
AFAIK, the pinctrl in tied to the
On 11 April 2014 01:31, Tim Kryger tim.kry...@linaro.org wrote:
When an external regulator provides VDD, set ocr_avail directly based on
the supported voltage range. This allows for the use of regulators that
can't provide exactly 1.8v, 3.0v, or 3.3v and ensures that ocr_avil bits
are only
From: Roger Tseng rogera...@realtek.com
This patchset adds modules to support Realtek USB vendor specific class
flash
card reader: one base module in MFD subsystem and two host modules in both
mmc
and memstick subsystems. The architecture is similar to rtsx_pci.
This work is
On Fri, 2014-04-11 at 11:28 +0100, Lee Jones wrote:
From: Roger Tseng rogera...@realtek.com
This patchset adds modules to support Realtek USB vendor specific class
flash
card reader: one base module in MFD subsystem and two host modules in
both mmc
and memstick subsystems.
This series contains the change for selection of bus speed mode.
Previous implementation is complicated and some sequence is duplicated.
And specially, HS400 mode eMMC5.0 is introduced this time.
This patch-set has been tested in Exynos SoC.
Note:
This patch-set depends on [PATCH RESEND v3 1/7]
Timing mode identifier has same role and can take the place
of speed mode. This change removes all related speed mode.
Signed-off-by: Seungwon Jeon tgih@samsung.com
Acked-by: Ulf Hansson ulf.hans...@linaro.org
Tested-by: Jaehoon Chung jh80.ch...@samsung.com
Acked-by: Jaehoon Chung
Current implementation for bus speed mode selection is too
complicated. This patch is to simplify the codes and remove
some duplicate parts.
The following changes are including:
* Adds functions for each mode selection(HS, HS-DDR, HS200 and etc)
* Rearranged the mode selection sequence with
This patch adds HS400 mode support for eMMC5.0 device.
HS400 mode is high speed DDR interface timing from HS200.
Clock frequency is up to 200MHz and only 8-bit bus width is
supported. In addition, tuning process of HS200 is required
to synchronize the command response on the CMD line because
CMD
Power class is changed once only after selection of bus modes
including speed and bus-width finishes finally.
Signed-off-by: Seungwon Jeon tgih@samsung.com
Tested-by: Jaehoon Chung jh80.ch...@samsung.com
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
Acked-by: Ulf Hansson
Device types which are supported by both host and device
can be identified when EXT_CSD is read. There is no need to
check host's capability anymore.
Signed-off-by: Seungwon Jeon tgih@samsung.com
Tested-by: Jaehoon Chung jh80.ch...@samsung.com
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
On 11 April 2014 13:34, Seungwon Jeon tgih@samsung.com wrote:
Device types which are supported by both host and device
can be identified when EXT_CSD is read. There is no need to
check host's capability anymore.
Signed-off-by: Seungwon Jeon tgih@samsung.com
Tested-by: Jaehoon Chung
On 11 April 2014 13:34, Seungwon Jeon tgih@samsung.com wrote:
This patch adds HS400 mode support for eMMC5.0 device.
HS400 mode is high speed DDR interface timing from HS200.
Clock frequency is up to 200MHz and only 8-bit bus width is
supported. In addition, tuning process of HS200 is
On Fri, Apr 11, 2014 at 1:15 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 11 April 2014 01:31, Tim Kryger tim.kry...@linaro.org wrote:
+static unsigned int sdhci_get_ocr_avail_from_vmmc(struct sdhci_host *host)
+{
+ unsigned int ocr_avail = 0;
+ struct regulator *vmmc =
Change the patch version number from V4 to v5
The Field Firmware Update (FFU) feature is new for eMMC 5.0 spec
(Jedec: JESD84-B50.pdf)
http://www.jedec.org/standards-documents/technology-focus-areas/flash-memory-ssds-ufs-emmc/e-mmc
An ioctl has been added to provide the new firmware image's
On 9 April 2014 01:56, Ulf Hansson ulf.hans...@linaro.org wrote:
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 098374b..ff7fd2e 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -2421,6 +2421,11 @@ void mmc_rescan(struct work_struct *work)
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