On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is used in mmci
driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
(...)
+
On Mon, May 12, 2014 at 10:02 PM, Seungwon Jeon tgih@samsung.com wrote:
As I mentioned in previous version, you put all reset stuff in existing
fifo_reset function.
Although databook mentions ciu_reset case for SBE error, it's not obvious
when ciu_reset is needed in other error cases.
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit postion datactrl[16:4] hold the true block size instead of power
of 2.
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
domain so subsequent writes to registers will be ignored until 3 clock cycles
have
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch moves some of the ST specific register extensions access under
condition, so that other SOCs like Qualcomm or ARM would not a side effect of
writing to
On 12 May 2014 16:33, Konstantin Dorfman kdorf...@codeaurora.org wrote:
Hello Chris, Ulf,
Sorry for nagging.
No worries. Let me have some more thinking before I come back to you though.
Kind regards
Ulf Hansson
Do you have opinion on issue with retries counter for data command?
Since
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK register layout is bit different to the standard pl180 register layout.
Qcom SDCC controller some setup in MCICLK register to get it going. So this
patch
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of
On Tue, Apr 29, 2014 at 10:21 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Some bits which control Command Path State Machine (CPSM) are new in Qcom
integration, so this patch adds support to those bits.
Signed-off-by: Srinivas
On Tue, Apr 29, 2014 at 10:21 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still
On Monday 12 May 2014 18:38:41 Sonny Rao wrote:
+#ifndef CONFIG_MMC_DW_IDMAC
+ if (host-use_dma)
+ flags |= SDMMC_CTRL_DMA_RESET;
+#endif
Can you change the above like this?
if (IS_ENABLED(CONFIG_MMC_DW_IDMAC) host-use_dma)
flags |=
On 13 May 2014 00:23, Chris Ball ch...@printf.net wrote:
Hi Ulf,
On Thu, May 08 2014, Ulf Hansson wrote:
Note 2)
I have not included the patch below; since I think it would be better
if you just drop the patch which this is reverting from your mmc next
branch.
[PATCH 1/2] mmc: rtsx: Revert
Thanks Linus W.
On 13/05/14 08:17, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but
Thanks Linus W for reviewing the patches.
On 13/05/14 08:29, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
On 13/05/14 08:20, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
On 13/05/14 09:08, Linus Walleij wrote:
/* Keep ST Micro busy mode if enabled */
- datactrl |= host-datactrl_reg MCI_ST_DPSM_BUSYMODE;
+ if (host-hw_designer == AMBA_VENDOR_ST)
+ datactrl |= host-datactrl_reg MCI_ST_DPSM_BUSYMODE;
Do not hard-check the
Thanks Linus W.
On 13/05/14 09:19, Linus Walleij wrote:
Again follow the pattern of storing register templates in the vendor_data
struct. I think you will quickly realize how this can be cut down with
new fields like .clk_4bitmode etc.
/* Modified PL180 on Versatile Express platform */
Thanks Linus W,
On 13/05/14 09:28, Linus Walleij wrote:
code is conditioned on hw designer.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
(...)
+ if (host-hw_designer == AMBA_VENDOR_QCOM) {
+ host-cclk = host-mclk;
+ }
Thanks Linus W,
On 13/05/14 08:16, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is used in mmci
driver.
Signed-off-by:
On 13/05/14 09:34, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:21 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register
On 29 April 2014 10:18, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Hi Russell,
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register
On 13/05/14 11:04, Ulf Hansson wrote:
On 29 April 2014 10:18, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Hi Russell,
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit
Hi,
On 12/05/14 22:44, Sonny Rao wrote:
Doug mentioned that James Hogan might have an answer. James, are
there Imgtec SoCs which use dw_mmc and use DMA but don't use the
IDMAC? If so, we can add that support into this reset procedure
patch.
Yes, the Toumaz TZ1090 SoC has the dw_mmc
On Tuesday, May 13, Sonny Rao wrote:
On Mon, May 12, 2014 at 10:02 PM, Seungwon Jeon tgih@samsung.com wrote:
As I mentioned in previous version, you put all reset stuff in existing
fifo_reset function.
Although databook mentions ciu_reset case for SBE error, it's not obvious
when
Hi Jaehoon,
I think we can remove MMC_CAP_ERASE from host's cap.
Can you check below patch?
[PATCH v4] mmc: remove MMC_CAP_ERASE to enable trim in eMMC/SD Device
Thanks,
Seungwon Jeon
On Mon, May 12, 2014, Jaehoon Chung wrote:
To use the erase command, add the MMC_CAP_ERASE capability by
Hello.
On 05/13/2014 05:38 AM, Simon Horman wrote:
I've spent a couple of days with the driver just hanging due to me forgetting
to specify the external crystal frequency, so that clk_get_rate() returned 0
and thus the loop in tmio_mmc_set_clock() never ended. I don't think that's an
Hi, Seungwon.
On 05/13/2014 08:15 PM, Seungwon Jeon wrote:
Hi Jaehoon,
I think we can remove MMC_CAP_ERASE from host's cap.
Thanks for reminding. :)
It's my mistake..Confused with linux-3.10.
Best Regards,
Jaehoon Chung
Can you check below patch?
[PATCH v4] mmc: remove MMC_CAP_ERASE
Seungwon,
On Mon, May 12, 2014 at 9:52 PM, Seungwon Jeon tgih@samsung.com wrote:
Hi Doug,
On Tue, May 13, 2014, Doug Anderson wrote:
Seungwon,
On Sat, May 10, 2014 at 7:11 AM, Seungwon Jeon tgih@samsung.com wrote:
On Fri, May 09, 2014, Sonny Rao wrote:
On Thu, May 8, 2014 at
On Tue, May 13, 2014 at 04:09:57PM +0400, Sergei Shtylyov wrote:
Hello.
On 05/13/2014 05:38 AM, Simon Horman wrote:
I've spent a couple of days with the driver just hanging due to me
forgetting
to specify the external crystal frequency, so that clk_get_rate() returned 0
and thus the
On 05/13, Srinivas Kandagatla wrote:
Thanks Linus W,
On 13/05/14 08:16, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is
On Wed, May 7, 2014 at 1:35 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 7 May 2014 03:52, Nick Sanders nsand...@chromium.org wrote:
This patch removes an unneccesary 1ms mdelay in the HS200 tuning
loop, called 40 times per retuning. Currently this causes a latency
of 40ms on any emmc
Hi,
On Wed, May 14 2014, Grant Grundler wrote:
The delay is left in place for SD Cards, which use
MMC_SEND_TUNING_BLOCK rather than MMC_SEND_TUNING_BLOCK_HS200.
I'm not able to find evidence that this is required for SD in the
specs I have access to, however this delay has been present from
Hi, Dinh.
On 05/13/2014 12:48 AM, Dinh Nguyen wrote:
On Mon, 2014-05-12 at 20:14 +0900, Jaehoon Chung wrote:
Remove the support-highspeed property in dw-mmc.
support-highspeed property can be replaced to cap-sd/mmc-highspeed.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
On 05/13/2014 02:43 AM, Dinh Nguyen wrote:
On Mon, 2014-05-12 at 20:14 +0900, Jaehoon Chung wrote:
Remove the support-highspeed property in dw-mmc.
support-highspeed property can be replaced to cap-sd/mmc-highspeed.
s/support-highspeed/supports-highspeed
Will fix.
Dinh
--
To
36 matches
Mail list logo
