dw_mci_pltfm_remove() is not (nor should it be) marked as __exit,
so we should not be using __exit_p() wrapper with it.
Signed-off-by: Dmitry Torokhov
---
drivers/mmc/host/dw_mmc-exynos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drive
dw_mci_pltfm_remove() is not (nor should it be) marked as __exit,
so we should not be using __exit_p() wrapper with it.
Signed-off-by: Dmitry Torokhov
---
drivers/mmc/host/dw_mmc-rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c
b/
Hello Ulf,
On Fri, Jan 23, 2015 at 6:01 PM, Ulf Hansson wrote:
>>
>> Any reason to not use the devm_gpiod_get_index() managed version instead?
>
> This struct device don't have a bound driver to it. Thus this device
> won't be freed automagically from the ->remove() or failed ->probe()
> path.
>
On 23 January 2015 at 16:56, Javier Martinez Canillas
wrote:
> Hello Ulf,
>
> On Mon, Jan 19, 2015 at 10:13 AM, Ulf Hansson wrote:
>>
>> int mmc_pwrseq_simple_alloc(struct mmc_host *host, struct device *dev)
>> {
>> struct mmc_pwrseq_simple *pwrseq;
>> + int ret = 0;
>>
>>
The Device Tree description of SDHCI on Armada 388 RD board was
missing. This commit adds the node for it.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-388-rd.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/armada-388-rd.dts
b/arch/arm/boot/d
Instead of hardcoding the values of the interrupt flags, use the
macros provided by
and for the
Armada 38x SDHCI node.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-38x.dtsi
b/a
The SDHCI unit used on the Armada 38x needs using an extra register to
do specific clock adjustments in order to support the SDR50 and DDR50
modes. This patch extends the binding to allow using this register.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
From: Marcin Wojtas
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register.
This commit add the support of this register and for SDR50 or DDR50
mode use it as suggested by the erratum:
- Set the SDIO3 Clock Inv field in SDI
The binding of the armada-380-sdhci has been extended with a new
register in order to be able to use the SDR50 and DDR50 mode. This
commit add the resource associated to this new register for the
Armada 38x.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 5 -
1 file c
Hi,
this series brings fixes and improvements for the SDHCI controller of
the Armada 38x SoCs.
The changes for this third version was done on the second patch, see
the changelog for the details.
The first two patches are fixes and should be also applied on the
stable branch (I added stable in co
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not
From: Marcin Wojtas
According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
different capabilities than the ones shown in its registers:
- it doesn't support the voltage switching: it can work either with
3.3V or 1.8V supply
- it doesn't support the SDR104 mode
- SDR50 mode doesn't
Hello Ulf,
On Mon, Jan 19, 2015 at 10:13 AM, Ulf Hansson wrote:
>
> int mmc_pwrseq_simple_alloc(struct mmc_host *host, struct device *dev)
> {
> struct mmc_pwrseq_simple *pwrseq;
> + int ret = 0;
>
> pwrseq = kzalloc(sizeof(struct mmc_pwrseq_simple), GFP_KERNEL);
>
Hi Marcin,
On 23/01/2015 12:33, Marcin Wojtas wrote:
> Dear Gregory,
>
>
>> @@ -118,8 +118,11 @@ static int mv_conf_mbus_windows(struct platform_device
>> *pdev,
>> return 0;
>> }
>>
>> -static int armada_38x_quirks(struct sdhci_host *host)
>> +static int armada_38x_quirks(struct platf
On 21 January 2015 at 11:17, Pramod Gurav wrote:
> DMA configuration has been removed from function mmci_dma_setup but the
> local mask variable was not removed. This remains unused hence remove
> it from the function and operations on it
>
> Signed-off-by: Pramod Gurav
Thanks! Applied for next.
On 23 January 2015 at 11:08, Jisheng Zhang wrote:
> This patch is to fix a race condition that may cause an unhandled irq,
> which results in big sdhci interrupt numbers and endless "mmc1: got irq
> while runtime suspended" msgs before v3.15.
>
> Consider following scenario:
>
> CPU0
Dear Gregory,
> @@ -118,8 +118,11 @@ static int mv_conf_mbus_windows(struct platform_device
> *pdev,
> return 0;
> }
>
> -static int armada_38x_quirks(struct sdhci_host *host)
> +static int armada_38x_quirks(struct platform_device *pdev,
> +struct sdhci_host
Hi Mark
2015-01-23 12:03 GMT+01:00 Mark Rutland :
> [...]
>
>> + /*
>> + * According to erratum 'ERR-7878951' Armada 38x SDHCI
>> + * controller has different capabilities than the ones shown
>> + * in its registers
>> + */
>> + host->caps = sdhci_readl(host, SDHCI_CAPA
[...]
> + /*
> + * According to erratum 'ERR-7878951' Armada 38x SDHCI
> + * controller has different capabilities than the ones shown
> + * in its registers
> + */
> + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
> + if (of_get_property(np, "no-1-8-v", NULL)
The binding of the armada-380-sdhci has been extended with a new
register in order to be able to use the SDR50 and DDR50 mode. This
commit add the resource associated to this new register for the
Armada 38x.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 5 -
1 file c
Instead of hardcoding the values of the interrupt flags, use the
macros provided by
and for the
Armada 38x SDHCI node.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-38x.dtsi
b/a
From: Marcin Wojtas
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register.
This commit add the support of this register and for SDR50 or DDR50
mode use it as suggested by the erratum:
- Set the SDIO3 Clock Inv field in SDI
From: Marcin Wojtas
According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
different capabilities than the ones shown in its registers:
- it doesn't support the voltage switching: it can work either with
3.3V or 1.8V supply
- it doesn't support the SDR104 mode
- SDR50 mode doesn't
Hi,
this series brings fixes and improvements for the SDHCI controller of
the Armada 38x SoCs.
The main change for this second version was to put back the authorship
on patch 2 and 4 from Marcin as I ported them a 3.10 kernel.
The first two patches are fixes and should be also applied on the
sta
The Device Tree description of SDHCI on Armada 388 RD board was
missing. This commit adds the node for it.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-388-rd.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/armada-388-rd.dts
b/arch/arm/boot/d
According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not
The SDHCI unit used on the Armada 38x needs using an extra register to
do specific clock adjustments in order to support the SDR50 and DDR50
modes. This patch extends the binding to allow using this register.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
This patch is to fix a race condition that may cause an unhandled irq,
which results in big sdhci interrupt numbers and endless "mmc1: got irq
while runtime suspended" msgs before v3.15.
Consider following scenario:
CPU0CPU1
sdhci_px
Dear Ulf,
On Fri, 23 Jan 2015 00:23:29 -0800
Ulf Hansson wrote:
> On 21 January 2015 at 13:45, Jisheng Zhang wrote:
> > This patch is to fix a race condition that may cause an unhandled irq,
> > which results in big sdhci interrupt numbers and endless "mmc1: got irq
> > while runtime suspended"
On 21 January 2015 at 13:45, Jisheng Zhang wrote:
> This patch is to fix a race condition that may cause an unhandled irq,
> which results in big sdhci interrupt numbers and endless "mmc1: got irq
> while runtime suspended" msgs before v3.15.
>
> Consider following scenario:
>
> CPU0
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