[PATCH v3 0/2] regulator: Fix pbias regulator enable

vsel_reg and enable_reg of the pbias regulator descriptor should actually have the offset from syscon. However after "ARM: dts: : add minimal l4 bus layout with control module support" vsel_reg and enable_reg started to have the absolute address because of address translation that happens due to

[PATCH v3 2/2] ARM: dts: : use "ti,pbias-" compatible string for pbias

Use platform specific compatible strings instead of the common "ti,pbias-omap" compatible string. Signed-off-by: Kishon Vijay Abraham I Acked-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi |2 +- arch/arm/boot/dts/omap2430.dtsi |2 +-

[PATCH v3 1/2] regulator: pbias: program pbias register offset in pbias driver

Add separate compatible strings for every platform and populate the pbias register offset in the driver data. This helps avoid depending on the dt for pbias register offset. Also update the dt binding documentation with the new compatible strings. Suggested-by: Tony Lindgren

Re: [PATCH] ARM: multi_v7_defconfig: Enable PBIAS regulator

Hi, On Thursday 03 September 2015 08:53 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [150903 02:58]: >> PBIAS regulator is required for MMC module in OMAP2, OMAP3, OMAP4, >> OMAP5 and DRA7 SoCs. Enable it here. >> >> Signed-off-by: Kishon Vijay Abraham I >

Re: [PATCH v3 0/2] regulator: Fix pbias regulator enable

On 4 September 2015 at 14:00, Kishon Vijay Abraham I wrote: > vsel_reg and enable_reg of the pbias regulator descriptor should actually > have the offset from syscon. > > However after > "ARM: dts: : add minimal l4 bus layout with control module > support" > vsel_reg and enable_reg

[PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock

Different bus clock may need different pin setting. For example, fast bus clock like 208Mhz need pin drive fast while slow bus clock prefer pin drive slow to guarantee signal quality. So this patch creates two states, - Default (slow/normal) pin state - And fast pin state for higher freq bus

[PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields

IN case of Marvell 1928 family of devices, the SD_BUS_POWER and SD_BUS_VLT bits are used internally to gate the clocks, so we have to set these fields. Pasting Spec words here, The and fields should be configured to correct values. These actually do not do the voltage selection or switch power

[PATCH 2/5] mmc: sdhci-pxav3: Add platform specific set_clock ops

In case of PXA1928 & family of devices, the TX BUS and internal clock need to be set as part of ->set_clock() ops, so this patch adds platform specific ->set_clock() operation. Note that, in order to not break other platforms, this patch introduced the flag, which controls whether

[PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller

PXA1928 SDHCI controller has few differences, for example, PXAxxxPXA1928 ===== SDCLK_DELAY field 0x10A 0x114 SDCLK_DELAY mask0x1F

[PATCH 1/5] mmc: sdhci-pxav3: Enable pxa1928 device support

SDHCI controller present in PXA1928 has few differences as far as register map is concerned. For example, PXAxxxPXA1928 ===== SDCLK_DELAY field 0x10A 0x114 SDCLK_DELAY

[PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support

From: Kevin Liu IN case of MMC HS200 mode, current code does not enable SD_CE_ATA_2.MMC_HS200 & SD_CE_ATA_2.MMC_CARD bit configurations. So this patch updates the above bit fields correctly. Signed-off-by: Tim Wang Signed-off-by: Kevin Liu

Re: [PATCH v3 1/2] regulator: pbias: program pbias register offset in pbias driver

On Fri, Sep 04, 2015 at 05:30:24PM +0530, Kishon Vijay Abraham I wrote: > Add separate compatible strings for every platform and populate the > pbias register offset in the driver data. > This helps avoid depending on the dt for pbias register offset. If there are any changes from the already