On Fri, Oct 16, 2015 at 12:40 AM, Sergei Shtylyov
wrote:
> Renesas R8A7794 SoC also has the MMCIF controller...
>
> Signed-off-by: Sergei Shtylyov
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...
On Fri, Oct 16, 2015 at 12:39 AM, Sergei Shtylyov
wrote:
> The "compatible" property text contradicts even the example given in the MMCIF
> binding document itself; moreover, the Renesas MMCIF driver only matches on
> the generic "compatible" string and doesn't look for the SoC specific strings
Renesas R8A7794 SoC also has the MMCIF controller...
Signed-off-by: Sergei Shtylyov
---
The patch is against Ulf Hansson's 'mmc.git' repo's 'next' branches plus the
patch I posted earlier today...
Changes in version 3:
- resolved reject.
Changes in version 2:
- deferred R8A7793 support to the
The "compatible" property text contradicts even the example given in the MMCIF
binding document itself; moreover, the Renesas MMCIF driver only matches on
the generic "compatible" string and doesn't look for the SoC specific strings
at all. Thus describe "renesas,sh-mmcif" as a fallback value.
F
On 12.10.2015 07:46, Jisheng Zhang wrote:
Commit 8afdc9cca27f ("mmc: sdhci-pxav3: Get optional core clock") adds
additional optional clock support, but the clock names isn't correct.
The current "io" clock is really the PXAv3 SDHCI IP's "core" clock
which is manadatory. The current "core" clock
Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
card detection. According to the SD sdandard this signal can be used for
this purpose combined with a pull-down resistor, implying inverted (active
high) polarization of a card detect. MMC standard does not support this
feature
On Marvell Armada 38x SoC's the MMC_CARD bit in SD_CE_ATA_1 register must
be set to 0x1 when a MMC card is supposed to work in DDR mode, or when
commands CMD11, CMD14 and CMD20 are used.
This commit enables the above for all MMC cards by modifying the host
registers during card initialization. It
Some sdhci hosts may require handling quirks during card initialization at
the time when its type is already known. Hence a new callback (init_card)
is added in sdhci_ops.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci.c | 9 +
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 10
When resuming from suspend on Armada 38x SoC MBus windows have to be
re-configured and for that purpose mv_conf_mbus_windows function needed
rework. MBus windows register base address obtaining was moved to
armada_38x_quirks function in order to be kept in pxa global structure,
because it is used d
The newest revisions of A388-GP (v1.5 and higher) support only
DAT3-based card detection. Revisions < v1.5 based on GPIO detection
via I2C expander, but this solution is supposed to be deprecated on
new boards. In order to satisfy all type of hardware this commit
changes card detection to use softw
Hi,
Thank you for reviewing the patches. According to your remarks and some
new ideas I prepared third patchset. I modified my HW and now I could
check operation when using all three modes of detection (polling, gpio
and dat3) - it all seems working fine. Any remarks will be wellcome.
Best regard
On Thu, 2015-10-15 at 11:17 +0200, Ulf Hansson wrote:
> [...]
>
> >> >
> >> > struct clk *src_clk;/* msdc source clock */
> >> > + struct clk *src_clk_parent; /* src_clk's parent */
> >> > + struct clk *hs400_src; /* 400Mhz source clock */
> >>
> >> Hmm, so you need to con
[...]
>> >
>> > struct clk *src_clk;/* msdc source clock */
>> > + struct clk *src_clk_parent; /* src_clk's parent */
>> > + struct clk *hs400_src; /* 400Mhz source clock */
>>
>> Hmm, so you need to control the upper level clocks. Can you elaborate
>> on why this is neede
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