[+cc Naveen]
On Wed, Jul 29, 2015 at 05:31:59PM +0530, Muni Sekhar wrote:
[ Please keep me in CC as I'm not subscribed to the list]
Hello,
We are using the “Virtex-5 FPGA Integrated Endpoint Block for PCI
Express” in Linux platform. It supports only a single-function(Header
Type, Bit 7
-off-by: Wan ZongShun vincent@amd.com
Acked-by: Bjorn Helgaas bhelg...@google.com
---
include/linux/pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 2f7b9a4..cb63a7b 100644
--- a/include/linux/pci_ids.h
+++ b/include
On Fri, Jun 20, 2014 at 10:13 AM, Chen, Alvin alvin.c...@intel.com wrote:
From: Derek Browne derek.bro...@intel.com
On Intel Quark, there is a SDIO host controller. This patch is added to
enable the SDIO host controller.
Signed-off-by: Derek Browne derek.bro...@intel.com
Signed-off-by:
Remove the check for slots == 0 because it can never be 0 here.
Found by Coverity (CID 744269).
Signed-off-by: Bjorn Helgaas bhelg...@google.com
---
drivers/mmc/host/sdhci-pci.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
On Sun, Jun 12, 2011 at 1:44 PM, Ram Pai linux...@us.ibm.com wrote:
Looks like the kernel; by default, tries to allocate mem resource of size
0x400 each to the BARs of the cardbus bridge. This cannot be satisfied
meeting all the constraints. The BIOS had not allocated the resource to
begin
