Hi Maxime,
El 17/07/14 06:08, Maxime Ripard escribió:
PLL6 out of reset is running at 2.4GHz, which is outside of its operating
boundaries.
Enforce its maximum frequency as set in the datasheet to make sure we stays
within these bounds.
Signed-off-by: Maxime Ripard
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arch/arm/boot/dts/sun
Hi Maxime,
El 17/07/14 06:08, Maxime Ripard escribió:
In the A13, the out of reset frequency for the PLL6 is too high to be actually
working.
Hence, we need to be able to lower down its frequency whenever we need to use
the clock to some acceptable frequency.
This patch adds two new properties
Hi,
El 06/05/14 15:51, Maxime Ripard escribió:
Hi Emilio,
On Fri, May 02, 2014 at 05:57:15PM +0200, Hans de Goede wrote:
From: Emilio López
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López
Signed-off-by: Hans de
Hi Hans,
El 22/04/14 08:01, Hans de Goede escribió:
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzendörfer and I have been
working on.
The first 2 patches are depenencies which should go in through the clk tree,
Mike can you pick these 2 up please ? :
"clk: sunxi: factors: automati
Hi Mike et al,
El 15/12/13 01:51, Mike Turquette escribió:
clk_set_phase has been proposed before and now may be the time to add
it. There are two things that need to be addressed:
1) what are the values for the phase? This needs to work for others that
must set clk phase, so we need to conside
