posely don't print errors in mmc_regulator_set_vqmmc().
There are cases where the MMC core will try several different
voltages and we don't want to pollute the logs.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drive
This allows the tuning code to run and use higher speeds on capable cards.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 7 ++-
arch/arm/boot/dts/rk3288-veyron.dtsi | 6 ++
2 files changed, 12 insertions(+), 1 deletion(-)
es
set by the hardware are good enough.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
Acked-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 13 +
1 file changed
From: Alexandru M Stan <ams...@chromium.org>
The drive/sample clocks can be phase shifted. The drive clock
could be used in a future patch to adjust hold times. The sample
clock is used for tuning.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko
We will shortly need the calculation of an ocr-bit to the actual
voltage in a second place too, so move it from mmc_regulator_set_ocr
to a common function mmc_ocrbitnum_to_vdd to make that possible.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drivers/mmc/core/core.
ing with the clock phase framework
ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices
Douglas Anderson (2):
mmc: core: Add mmc_regulator_set_vqmmc()
mmc: dw_mmc: Use mmc_regulator_set_vqmmc in
start_signal_voltage_switch
Heiko Stuebner (2):
mmc: core: move ocr-
ut has no sample_clk defined we'll return EIO with an error
message.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
Acked-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
drivers/mmc/host/dw_mmc-rockchip.c | 162
signal voltage is 3.3V. This ensures max
compatibility.
2. We get rid of a few more warnings when probing unsupported
voltages.
3. We get rid of some non-dw_mmc specific code in dw_mmc.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@s
Am Freitag, 9. Oktober 2015, 13:11:21 schrieb Doug Anderson:
> Hi,
>
> On Fri, Oct 9, 2015 at 10:19 AM, Doug Anderson
wrote:
> > Hi,
> >
> > On Fri, Oct 9, 2015 at 1:10 AM, Ulf Hansson
wrote:
> >> Dough, Heiko,
> >>
> >> This patchset seems to
00420c]=0x46c actual_degrees=86
After this:
set_phase(86) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86
set_phase(89) delay_nums=28 reg[0xf000420c]=0x470 actual_degrees=90
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
es
set by the hardware are good enough.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devic
posely don't print errors in mmc_regulator_set_vqmmc().
There are cases where the MMC core will try several different
voltages and we don't want to pollute the logs.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drive
recise variance-values of 44-77 instead of 40-80.
Fold in the actual removal of the monotonic requirement and adapt
patch message accordingly.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drivers/clk/rockchip/clk-mmc-phase.c | 45
1 file changed,
This allows the tuning code to run and use higher speeds on capable cards.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 7 ++-
arch/arm/boot/dts/rk3288-veyron.dtsi | 6 ++
2 files changed, 12 insertions(+), 1 deletion(-)
From: Alexandru M Stan <ams...@chromium.org>
The drive/sample clocks can be phase shifted. The drive clock
could be used in a future patch to adjust hold times. The sample
clock is used for tuning.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko
ut has no sample_clk defined we'll return EIO with an error
message.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drivers/mmc/host/dw_mmc-rockchip.c | 162 +
1 file changed, 162 inserti
in
start_signal_voltage_switch
Heiko Stuebner (1):
ARM: dts: rockchip: add tuning related settings to veyron devices
.../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 13 ++
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 7 +-
arch/arm/boot/dts/rk3288-veyron.dtsi | 6 +
arch/arm/boot/dts
signal voltage is 3.3V. This ensures max
compatibility.
2. We get rid of a few more warnings when probing unsupported
voltages.
3. We get rid of some non-dw_mmc specific code in dw_mmc.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <
Hi Jaehoon,
Am Mittwoch, 2. September 2015, 14:01:52 schrieb Jaehoon Chung:
> Hi, Heiko.
>
> On 09/01/2015 03:24 AM, Heiko Stuebner wrote:
> > From: Alexandru M Stan <ams...@chromium.org>
> >
> > Add ciu_drv, ciu_sample clocks and default-sample-phase. This will
in
start_signal_voltage_switch
Heiko Stuebner (1):
ARM: dts: rockchip: add tuning related settings to veyron devices
.../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 14 +-
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 7 +-
arch/arm/boot/dts/rk3288-veyron.dtsi | 6 +
arch/arm
From: Alexandru M Stan <ams...@chromium.org>
The drive/sample clocks can be phase shifted. The drive clock
could be used in a future patch to adjust hold times. The sample
clock is used for tuning.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko
recise variance-values of 44-77 instead of 40-80.
Fold in the actual removal of the monotonic requirement and adapt
patch message accordingly.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
drivers/clk/rockchip/clk-mmc-phase.c | 45
1 file changed,
ut has no sample_clk defined we'll return EIO with an error
message.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Convert to mmc_send_tuning()
Fold in from the ChromeOS-tree:
- mmc: dw_mmc: Change tuning to only 16 phases
- mmc: dw_mmc: Test more phases
Signed-off-by: Heiko
signal voltage is 3.3V. This ensures max
compatibility.
2. We get rid of a few more warnings when probing unsupported
voltages.
3. We get rid of some non-dw_mmc specific code in dw_mmc.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <
00420c]=0x46c actual_degrees=86
After this:
set_phase(86) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86
set_phase(89) delay_nums=28 reg[0xf000420c]=0x470 actual_degrees=90
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
This allows the tuning code to run and use higher speeds on capable cards.
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 7 ++-
arch/arm/boot/dts/rk3288-veyron.dtsi | 6 ++
2 files changed, 12 insertions(+), 1 deletion(-)
es
set by the hardware are good enough.
Signed-off-by: Alexandru M Stan <ams...@chromium.org>
Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/Docume
nstead of picking the lowest one in the range.
* We very purposely don't print errors in mmc_regulator_set_vqmmc().
There are cases where the MMC core will try several different
voltages and we don't want to pollute the logs.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-o
Am Montag, 17. August 2015, 12:34:09 schrieb Ulf Hansson:
[...]
- mmc-max_seg_size = mmc-max_req_size;
-#endif /* CONFIG_MMC_DW_IDMAC */
+ if (host-use_dma) {
+ mmc-max_segs = host-ring_size;
I expect this may cause a compiler error
Hi,
Am Freitag, 13. März 2015, 20:32:43 schrieb Jaehoon Chung:
Hi Doug,
Will apply. Thanks!
just to make sure, you'll take patches 1-3 and I'll take the dts change from
patch 4, right?
Thanks
Heiko
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