Quoting Peter Griffin (2015-01-20 07:32:41)
Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card
Quoting Ulf Hansson (2015-01-15 02:04:04)
On 15 January 2015 at 10:20, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On czw, 2015-01-15 at 09:20 +0100, Ulf Hansson wrote:
+ Mike, Stephen (Clock maintainers)
On 12 January 2015 at 10:23, Krzysztof Kozlowski
k.kozlow...@samsung.com
Quoting Maxime Ripard (2014-09-11 13:18:17)
The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.
This will cause issue when the client driver will never call the set_phase
function,
Quoting Maxime Ripard (2014-08-30 13:03:02)
The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.
This will cause issue when the client driver will never call the set_phase
function,
Quoting Maxime Ripard (2014-08-30 13:03:09)
The MMC clock we thought we had until now are actually not one but three
different clocks.
The main one is unchanged, and will have three outputs:
- The clock fed into the MMC
- a sample and output clocks, to deal with when should we
On Tue, Jun 24, 2014 at 8:52 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi Daniel,
[adding Ulf, Chris and Mike to the discussion]
On 24.06.2014 11:48, Daniel Drake wrote:
sdhci_s3c_set_clock is called from sdhci_do_set_ios with interrupts
disabled, and this calls into
Quoting Linus Torvalds (2014-06-10 14:50:59)
On Tue, Jun 10, 2014 at 12:51 PM, Chris Ball ch...@printf.net wrote:
These patches have been tested in
linux-next, and there are three minor conflicts which I've resolved on
my mmc-updates-for-3.16-rc1-merged branch.
Your merged branch is
Quoting Hans de Goede (2014-05-02 08:57:14)
The first 2 patches are depenencies which should go in through the clk tree,
Mike can you pick these 2 up please ? :
Taken into clk-next.
clk: sunxi: factors: automatic reparenting support
Is uncontroversial and has been favorably reviewed by
Quoting Zhangfei Gao (2014-01-13 01:37:32)
Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Quoting Dinh Nguyen (2014-01-15 04:36:52)
Hi Mike,
Can you apply this to your clk tree?
The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
3.14-rc1?
Thanks,
Mike
Thanks,
Dinh
--
To unsubscribe from
Quoting Seungwon Jeon (2014-01-17 08:10:23)
On Sat, Jan 18, 2014 at 12:01 AM, Chris Ball ch...@printf.net wrote:
Hi,
On Tue, Jan 14 2014, Seungwon Jeon wrote:
On Monday, January 13, 2014, Zhangfei Gao wrote:
Remove clk_table and directly use ios-clock as clock source rate.
Quoting Haojian Zhuang (2014-01-14 21:59:40)
On 01/15/2014 11:53 AM, Mike Turquette wrote:
Quoting zhangfei (2014-01-14 17:40:25)
Dear Mike
On 01/15/2014 04:17 AM, Mike Turquette wrote:
Quoting Zhangfei Gao (2014-01-13 01:14:28)
Suggest by Arnd: abstract mmc tuning as clock behavior
Quoting Zhangfei Gao (2014-01-13 01:14:28)
Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Quoting zhangfei (2014-01-14 17:40:25)
Dear Mike
On 01/15/2014 04:17 AM, Mike Turquette wrote:
Quoting Zhangfei Gao (2014-01-13 01:14:28)
Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks
Quoting zhangfei (2013-12-14 18:18:45)
Dear Arnd
On 12/15/2013 05:33 AM, Arnd Bergmann wrote:
On Thursday 12 December 2013, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Add a altr,socfpga-sdmmc-sdr-clk clock type in the SOCFPGA clock driver.
This
clock type is
Quoting Heiko Stübner (2013-06-11 04:29:32)
SoCs like the Rockchip Cortex-A9 ones contain divider some clocks
that use the regular mechanisms for storage but allow only even
dividers and 1 to be used.
Therefore add a flag that lets _is_valid_div limit the valid dividers
to these values.
Quoting Heiko Stübner (2013-06-11 04:31:31)
This adds basic support for clocks on Rockchip rk3066 SoCs.
The clock handling thru small dt nodes is heavily inspired by the
sunxi clk code.
The plls are currently read-only, as their setting needs more
investigation. This also results in slow
17 matches
Mail list logo
