by default as it does not go thru the driver core.
This patch adds a call to pinctrl_bind_pins() to bind pins which
are going to be used as gpios.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/core/pwrseq.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/core/pwrseq.c b/d
(e5943004)
---[ end trace 80b84017d7c9e7e5 ]---
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/core/pwrseq_simple.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
index e9f1d8d..6f0a875 100644
--- a
Hi Javier,
You are in a lead of 3 hrs from me..
Surprisingly I send very much same patch just few Mins ago :-)
May be we can merge goods in both :-)
On 28/01/15 10:10, Javier Martinez Canillas wrote:
Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence. F
On 28/01/15 13:35, Ulf Hansson wrote:
On 28 January 2015 at 14:16, Srinivas Kandagatla
wrote:
This patchset adds support to reset/powerup multiple gpio pins on a given
sdio bus. The use case is simple, on sdio we could have multiple devices
like WLAN, BT which are controlled by there own
On 28/01/15 10:10, Javier Martinez Canillas wrote:
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas
---
Documentation/devicetree/bindings/mmc/mmc-pwrseq-
On 28/01/15 16:13, Javier Martinez Canillas wrote:
Hello Srinivas,
Thanks a lot for your feedback.
On 01/28/2015 03:01 PM, Srinivas Kandagatla wrote:
Hi Javier,
You are in a lead of 3 hrs from me..
Surprisingly I send very much same patch just few Mins ago :-)
:-)
I didn't fin
could not get BT and WLAN working at same time on IFC6410.
Thanks,
srini
Srinivas Kandagatla (2):
mmc: pwrseq: Add support to control multiple gpios in simple pwrseq
mmc: pwrseq: Update document with multiple gpios support
.../devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 7 ++-
drivers/mmc
not get BT and WLAN working at same time on IFC6410.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/core/pwrseq_simple.c | 64
1 file changed, 45 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core
This patch updates the text and examples the mmc pwrseq document with multiple
gpios support. Typical example is WLAN and BT chips on SDIO bus.
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 7 ---
1 file changed, 4 insertions(+), 3
Reported-by: Nicolas Dechesne
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/core/core.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index d03a080..4d9b142 100644
--- a/drivers/mmc/core/core.c
+++ b
cf6cb3f6432c9834 ]---
Kernel panic - not syncing: Fatal exception in interrup
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 264c947..84f4a91 100644
--- a/drivers/mmc/h
--srini
Srinivas Kandagatla (2):
mmc: core: fix prepared requests while doing bkops
mmc: mmci: fix mmci_post_request
drivers/mmc/core/core.c | 12 +++-
drivers/mmc/host/mmci.c | 7 +++
2 files changed, 18 insertions(+), 1 deletion(-)
--
1.9.1
--
To unsubscribe from this list
Hi Pramod,
Thankyou for the patches.
You should be aware that this driver is due to be *Removed* very soon.
Basically msm_sdcc is a hacked version of mmci driver.
From v3.17 mmci driver added support for qualcomm specific
customization to pl180.
So msm platform should be able to use pl180 mmci
Hi Ulf,
On 10/09/14 08:58, Ulf Hansson wrote:
On 22 August 2014 06:54, Srinivas Kandagatla
wrote:
From: Ulf Hansson
For the ux500v2 variant of the PL18x block, any block sizes are
supported. This will make it possible to decrease data overhead
for SDIO transfers.
This patch is based on Ulf
l_pipe_index(np, "tx");
129 producer_id = of_get_dml_pipe_index(np, "rx");
130
131 if (producer_id < 0 || consumer_id < 0)
^^
132
Reported-by: Dan Carpenter
Signed-off-by: Srinivas Kandagatl
Hi Dan,
Thankyou for reporting this warning.
Both consumer_id and producer_id are supposed to be int instead of u32.
I will fix this.
Thanks,
srini
On 28/08/14 14:21, Dan Carpenter wrote:
Hello Srinivas Kandagatla,
The patch 4dd5a1e6dd12: "mmc: mmci: Add qcom dml support to the
d
SOC.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 48
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index a25759e..264c947 100644
--- a/drivers/mmc/host/mmci.c
the issue.
Originally the issue is detected while testing WLAN ath6kl on Qualcomm
APQ8064.
Reviewed-by: Linus Walleij
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b
From: Ulf Hansson
For the ux500v2 variant of the PL18x block, any block sizes are
supported. This will make it possible to decrease data overhead
for SDIO transfers.
This patch is based on Ulf Hansson patch
http://www.spinics.net/lists/linux-mmc/msg12160.html
Signed-off-by: Srinivas Kandagatla
this is already fixed by original patch from Ulf.
Changes since RFC:
- moved sdio flag to st_sdio to simplify the checks.
- use Ulf's patch to address IP's which support anysize blocks.
Thanks,
srini
Srinivas Kandagatla (2):
mmc: mmci: Add sdio enable mask in variant da
On 19/08/14 12:55, Ulf Hansson wrote:
writel(host->size, base + MMCIDATALENGTH);
>
>- blksz_bits = ffs(data->blksz) - 1;
>- BUG_ON(1 << blksz_bits != data->blksz);
I don't like this BUG_ON at all, I would prefer if we remove it. The
original patch "mmc: mmci: Support any b
SOC.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 48
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index fc08203..26aa443 100644
--- a/drivers/mmc/host/mmci.c
Changes since RFC:
- moved sdio flag to st_sdio to simplify the checks.
- use Ulf's patch to address IP's which support anysize blocks.
Thanks,
srini
Srinivas Kandagatla (3):
mmc: mmci: move block size validation under relevant code
mmc: mmci: Add sdio enable mas
From: Ulf Hansson
For the ux500v2 variant of the PL18x block, any block sizes are
supported. This will make it possible to decrease data overhead
for SDIO transfers.
This patch is based on Ulf Hansson patch
http://www.spinics.net/lists/linux-mmc/msg12160.html
Signed-off-by: Srinivas Kandagatla
the issue.
Originally the issue is detected while testing WLAN ath6kl on Qualcomm
APQ8064.
Reviewed-by: Linus Walleij
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b
Qualcomm APQ8064 SOC.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3089fba..1c99195 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host
Thankyou Linus for the feedback.
On 13/08/14 09:58, Linus Walleij wrote:
On Tue, Aug 12, 2014 at 2:05 PM, Srinivas Kandagatla
wrote:
From: Srinivas Kandagatla
This patch moves ST specific sdio setup under a vendor id condition,
this will ensure that the ST specfic setup is not done on
Thankyou for the feedback.
On 12/08/14 15:12, Russell King - ARM Linux wrote:
On Tue, Aug 12, 2014 at 01:04:40PM +0100, Srinivas Kandagatla wrote:
From: Srinivas Kandagatla
This patch adds condition in mmci_validate_data to skip checking
blocksize for SDIO card types. SDIO card type can
From: Srinivas Kandagatla
This patch adds sdio enable mask in variant data, SOCs like ST have
special bits in datactrl register to enable sdio. Unconditionally setting
this bit in this driver breaks other SOCs like Qualcomm which maps this
bits to something else, so making this enable bit to
From: Srinivas Kandagatla
This patch moves ST specific sdio setup under a vendor id condition,
this will ensure that the ST specfic setup is not done on other vendor
like Qualcomm.
Originally the issue was detected while testing WLAN ath6kl on IFC6410
board with APQ8064 SOC.
Signed-off-by
From: Srinivas Kandagatla
This code moves a BUG_ON condition to relevant if block, this check is
not necessary for IPs which can set any arbitrary block size in a given
range.
This patch is necessary for SDIO which sets block sizes that are exactly
not power of 2.
Original issue detected while
From: Srinivas Kandagatla
This patch adds condition in mmci_validate_data to skip checking
blocksize for SDIO card types. SDIO card type can issue blocksizes
which are not exactly power of 2 so this check always fails, resulting
in SDIO failures.
Relaxing this check for SDIO in
From: Srinivas Kandagatla
This patchset fixes few sdio related issues encountered while testing
WLAN ath6kl via SDIO on IFC6410 board with Qualcomm APQ8064 SOC.
First patch "mmc: mmci: Enable SDIO support for Qualcomm variant data"
enables sdio support for Qualcom SOCs. I can move t
From: Srinivas Kandagatla
This patch sets sdio flag in qualcomm variant data to enable WLAN
connected via sdio on IFC6410 board.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
If its not too late, is it possible to queue this patch for v3.17?
---
srini
On 29/07/14 03:50, Srinivas Kandagatla wrote:
On Qualcomm APQ8064 SOCs, SD card controller has an additional glue
called DML (Data Mover Local/Lite) to assist dma transfers.
This hardware needs to be setup before any
.
Most of this code has been ported from qualcomm's 3.4 kernel.
This patch adds the code necessary to intialize the hardware and setup
before doing any dma transfers.
Reviewed-by: Linus Walleij
Signed-off-by: Srinivas Kandagatla
---
Changes since v3:
- moved copyright from Code Aurora to
.
Most of this code has been ported from qualcomm's 3.4 kernel.
This patch adds the code necessary to intialize the hardware and setup
before doing any dma transfers.
Reviewed-by: Linus Walleij
Signed-off-by: Srinivas Kandagatla
---
Changes since v2:
- copied missing memory barriers fro
On 23/07/14 23:58, Stephen Boyd wrote:
On 07/18/14 13:53, Srinivas Kandagatla wrote:
@@ -468,6 +473,11 @@ static void mmci_dma_setup(struct mmci_host *host)
if (max_seg_size < host->mmc->max_seg_size)
host->mmc->max_seg_size
.
Most of this code has been ported from qualcomm's 3.4 kernel.
This patch adds the code necessary to intialize the hardware and setup
before doing any dma transfers.
Signed-off-by: Srinivas Kandagatla
---
Changes since v1:
- Added licence text as spotted by Stephen B.
- Simplifie
Thanks Stephen for the comments.
On 18/07/14 00:06, Stephen Boyd wrote:
On 07/17/14 12:36, Srinivas Kandagatla wrote:
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index b66b351..a83b7b5 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -74,6 +75,7
On 17/07/14 20:36, Srinivas Kandagatla wrote:
On Qualcomm APQ8064 SOCs, SD card controller has an additional glue
called DML (Data Mover Local/Lite) to assist dma transfers.
This hardware needs to be setup before any dma transfer is requested.
DML itself is not a DMA engine, its just a gule
.
Most of this code has been ported from qualcomm's 3.4 kernel.
This patch adds the code necessary to intialize the hardware and setup
before doing any dma transfers.
Tested-by: Prakash Burla
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/Kconfig | 11 +++
drivers/mmc
On 11/07/14 14:49, Linus Walleij wrote:
On Fri, Jul 11, 2014 at 1:48 PM, Srinivas Kandagatla
wrote:
On Qualcomm APQ8064 SOCs, SD card controller has an additional glue
called DML (Data Mover Local/Lite) to assist dma transfers.
This hardware needs to be setup before any dma transfer is
.
Most of this code has been ported from qualcomm's 3.4 kernel.
This patch adds the code necessary to intialize the hardware and setup
before doing any dma transfers.
Signed-off-by: Srinivas Kandagatla
---
Hi All,
DMA support for Qualcomm SD card controller is missing in my last patchset
Hi Ulf,
On 11/06/14 18:35, Ulf Hansson wrote:
Thanks Srinivas, great work!
We didn't reach 3.16, but now I have applied this for my next branch
intended for 3.17.
That's great.
For you information, the v6 patchset needed a minor re-base, and one
of the patches had a checkpatch error. I ma
From: Srinivas Kandagatla
This patch adds a Qualcomm SD Card controller specific register variations
to header file. Qualcomm SDCC controller is pl180, with slight changes in
the register layout from standard pl180 register set.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.h
From: Srinivas Kandagatla
On Qcom SD Card controller POWER, CLKCTRL, DATACTRL and COMMAND registers
should be updated in MCLK domain, and writes to these registers must be
separated by three MCLK cycles. This resitriction is not applicable for
other registers. Any subsequent writes to these
From: Srinivas Kandagatla
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
---
drivers/mmc/host/mmci.c | 5 +++
From: Srinivas Kandagatla
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is updated with incorrect ddrmode mask,
resulting in failures on Qualcomm SD
From: Srinivas Kandagatla
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special case them.
Signed-off-by
From: Srinivas Kandagatla
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs.
Signed-off-by: Sri
From: Srinivas Kandagatla
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host CPU reads the MCIFIFO. With
From: Srinivas Kandagatla
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control flag in variant structure giving more flexibility
to
From: Srinivas Kandagatla
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-by
From: Srinivas Kandagatla
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code to
special case them
From: Srinivas Kandagatla
Some of the controller have maximum supported frequency, This patch adds
support in variant data structure to specify such restrictions. This
gives more flexibility in calculating the f_max before passing it to
mmc-core.
Signed-off-by: Srinivas Kandagatla
---
drivers
From: Srinivas Kandagatla
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
---
drivers/mmc/host/mmci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Srinivas Kandagatla
Thankyou Linus W, Ulf H, Russell K and everyone for reviewing RFC to v5 patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are
Thanks Russell,
On 31/05/14 13:35, Russell King - ARM Linux wrote:
because allegedly it makes it more "readable". I don't see much benefit
to this patch.
Ok, I will drop this patch in next version.
thanks,
srini
--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
the b
Thanks Russell,
On 31/05/14 13:29, Russell King - ARM Linux wrote:
>+ if ((host->variant->explicit_mclk_control) &&
>+ (ios->clock != host->clock_cache)) {
Please explain what use these parens have (or just get rid of them as
they're completely unnecessary - they do nothing for readabi
From: Srinivas Kandagatla
This patch adds a Qualcomm SD Card controller specific register variations
to header file. Qualcomm SDCC controller is pl180, with slight changes in
the register layout from standard pl180 register set.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.h
From: Srinivas Kandagatla
This patch converts the register bits in the header file to use BIT(()
macro, which looks much neater.
No functional changes done.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.h | 208
1 file changed
From: Srinivas Kandagatla
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is updated with incorrect ddrmode mask,
resulting in failures on Qualcomm SD
From: Srinivas Kandagatla
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
---
drivers/mmc/host/mmci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Srinivas Kandagatla
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
---
drivers/mmc/host/mmci.c | 5 +++
From: Srinivas Kandagatla
On Qcom SD Card controller POWER, CLKCTRL, DATACTRL and COMMAND registers
should be updated in MCLK domain, and writes to these registers must be
separated by three MCLK cycles. This resitriction is not applicable for
other registers. Any subsequent writes to these
From: Srinivas Kandagatla
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-by
From: Srinivas Kandagatla
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code to
special case them
From: Srinivas Kandagatla
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control flag in variant structure giving more flexibility
to
From: Srinivas Kandagatla
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs.
Signed-off-by: Sri
From: Srinivas Kandagatla
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host CPU reads the MCIFIFO. With
From: Srinivas Kandagatla
Some of the controller have maximum supported frequency, This patch adds
support in variant data structure to specify such restrictions. This
gives more flexibility in calculating the f_max before passing it to
mmc-core.
Signed-off-by: Srinivas Kandagatla
---
drivers
From: Srinivas Kandagatla
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special case them.
Signed-off-by
From: Srinivas Kandagatla
Thankyou Linus W, Ulf H and everyone for reviewing RFC to v4 patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are different to the
Hi Ulf,
Managed to reuse the existing mmci_pio_read function with some minor
modifications, Issue was with reading full fifo sizes which was creating
the issue.
On 30/05/14 12:44, Srinivas Kandagatla wrote:
That sounds sensible.. I will try it.
+ *ptr = readl(host
Hi Ulf,
On 30/05/14 12:27, Ulf Hansson wrote:
On 28 May 2014 15:48, wrote:
...
.f_max = 20800,
.explicit_mclk_control = true,
+ .qcom_fifo = true,
};
static int mmci_card_busy(struct mmc_host *mmc)
@@ -1006,6 +1009,40 @@ mmci_c
Thanks Ulf for reviewing.
On 30/05/14 11:25, Ulf Hansson wrote:
On 28 May 2014 15:47, wrote:
From: Srinivas Kandagatla
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in
Thanks Ulf,
On 30/05/14 11:28, Ulf Hansson wrote:
*/
>- if (host->mclk > 1) {
>- ret = clk_set_rate(host->clk, 1);
>+ if (host->mclk > host->variant->f_max) {
You can use the local variant pointer directly, instead of host->variant.
yes, Wil
On 30/05/14 10:55, Ulf Hansson wrote:
On 28 May 2014 15:47, wrote:
From: Srinivas Kandagatla
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also populates the Qcom variant data with
these new values specific to Qualcomm SD Card Controller
On 30/05/14 10:35, Ulf Hansson wrote:
On 28 May 2014 15:46, wrote:
From: Srinivas Kandagatla
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is
On 30/05/14 10:39, Ulf Hansson wrote:
On 28 May 2014 15:46, wrote:
From: Srinivas Kandagatla
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci a
Sorry Stephen for late reply,
Some reason this mail was filtered in other folders.
On 24/05/14 00:28, Stephen Boyd wrote:
On 05/23/14 05:53, srinivas.kandaga...@linaro.org wrote:
@@ -1022,6 +1025,40 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command
*cmd,
}
}
+static int mmc
From: Srinivas Kandagatla
This patch converts the register bits in the header file to use BIT(()
macro, which looks much neater.
No functional changes done.
Signed-off-by: Srinivas Kandagatla
---
drivers/mmc/host/mmci.h | 208
1 file changed
From: Srinivas Kandagatla
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs.
Signed-off-by: Sri
From: Srinivas Kandagatla
Some of the controller have maximum supported frequency, This patch adds
support in variant data structure to specify such restrictions. This
gives more flexibility in calculating the f_max before passing it to
mmc-core.
Signed-off-by: Srinivas Kandagatla
---
drivers
From: Srinivas Kandagatla
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also populates the Qcom variant data with
these new values specific to Qualcomm SD Card Controller.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
From: Srinivas Kandagatla
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host CPU reads the MCIFIFO. With
From: Srinivas Kandagatla
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control flag in variant structure giving more flexibility
to
From: Srinivas Kandagatla
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-by
From: Srinivas Kandagatla
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special case them.
Signed-off-by
From: Srinivas Kandagatla
On Qcom SD Card controller POWER, CLKCTRL, DATACTRL and COMMAND registers
should be updated in MCLK domain, and writes to these registers must be
separated by three MCLK cycles. This resitriction is not applicable for
other registers. Any subsequent writes to these
From: Srinivas Kandagatla
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is updated with wrong ddrmode mask on non
ST SOCs, resulting in card
From: Srinivas Kandagatla
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code to
special case them
From: Srinivas Kandagatla
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
---
drivers/mmc/host/mmci.c | 6
From: Srinivas Kandagatla
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Linus Walleij
---
drivers/mmc/host/mmci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Srinivas Kandagatla
Thankyou Linus W, Ulf H and everyone for reviewing RFC to v3 patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are different to the
Hi Ulf,
On 26/05/14 22:38, Srinivas Kandagatla wrote:
2 files changed, 28 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 17e7f6a..6434f5b1 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -185,6 +185,10 @@ static struct variant_data
On 28/05/14 09:08, Linus Walleij wrote:
On Fri, May 23, 2014 at 2:53 PM, wrote:
+ if (unlikely(bytes)) {
+ unsigned char buf[4];
(...)
Please think twice about this.
http://lwn.net/Articles/70473/
http://lwn.net/Articles/420019/
http://lwn.net/Articles/182369/
Tha
On 28/05/14 09:02, Linus Walleij wrote:
On Tue, May 27, 2014 at 12:39 AM, Srinivas Kandagatla
wrote:
On 26/05/14 15:21, Ulf Hansson wrote:
On 23 May 2014 14:52, wrote:
+ boolexplicit_mclk_control;
+ boolcclk_is_mclk;
I can'
Hi Linus W,
On 26/05/14 11:07, Ulf Hansson wrote:
unsigned intfifosize;
> unsigned intfifohalfsize;
>@@ -116,6 +118,7 @@ static struct variant_data variant_u300 = {
> .fifosize = 16 * 4,
> .fifohalfsize = 8 * 4,
>
1 - 100 of 196 matches
Mail list logo
