for certain Micron cards known to
have this problem.
Signed-off-by: Stefan Nilsson XK stefan.xk.nils...@stericsson.com
Signed-off-by: Ulf Hansson ulf.hans...@stericsson.com
---
drivers/mmc/card/block.c |7 +++
drivers/mmc/core/core.c | 12
include/linux/mmc/card.h |6
Corrects a bug in MMCI host driver which silently causes
small reads ( 4 bytes as only used in SDIO) from PL-18X to fail.
Signed-off-by: Stefan Nilsson XK stefan.xk.nils...@stericsson.com
Signed-off-by: Ulf Hansson ulf.hans...@stericsson.com
Acked-by: Linus Walleij linus.wall...@linaro.org
with a number of byte transfers.
When doing this change it was also possible to break out the quirk
for broken byte mode in a much cleaner way, and collect the logic of
when to do byte or block transfer in one function instead of two.
Signed-off-by: Stefan Nilsson XK stefan.xk.nils
On 10/07/2011 09:11 PM, Russell King - ARM Linux wrote:
But first, you need to fix your code so you're only reading 32-bit
quantities from the FIFO register.
Hi Russel, what to you think of doing it this way instead:
/*
* SDIO especially may want to send
Hi Russel,
On 10/01/2011 06:09 PM, Russell King - ARM Linux wrote:
Does this even work? From the MMCI spec, I see no way for the MMCI
peripheral to know the size of the read/write on the APB bus.
The APB bus signals the MMCI uses are:
PCLK - APB bus clock
PRESETn - APB bus reset
PADDR[11:2]
Hi Russel,
On 10/01/2011 06:12 PM, Russell King - ARM Linux wrote:
Shouldn't this also re-enable the ST hardware flow control for non-SDIO
cards?
I do not think that is needed. Hardware flow control is turned on per
default for all cards thanks to the .clkreg member of the variant struct:
Hi Aaron,
On 09/16/2011 04:05 AM, Aaron Lu wrote:
Hi Ulf,
I'm not familiar with mmc, but I've some questions on sd below.
On Thu, Sep 15, 2011 at 05:50:38PM +0200, Ulf Hansson wrote:
Earlier all cards where initiated with bus mode set as OPENDRAIN, and then
later switched to PUSHPULL.
