[PATCH] mmc: core: Prevent unexpected SD Clock gating during Signal Voltage Switch Procedure

2014-01-28 Thread Vincent Yang
When switching the signal voltage from 3.3V to 1.8V, there should be only one SD Clock gating and un-gating operation. Between them the SD host controller should switch signal level to 1.8V. However, sometimes there is an additional gating and un-gating operation immediately after CMD11. This

Re: [PATCH] mmc: core: Prevent unexpected SD Clock gating during Signal Voltage Switch Procedure

2014-01-28 Thread Ulf Hansson
On 28 January 2014 11:50, Vincent Yang vincent.yang.fuji...@gmail.com wrote: When switching the signal voltage from 3.3V to 1.8V, there should be only one SD Clock gating and un-gating operation. Between them the SD host controller should switch signal level to 1.8V. However, sometimes there