On 20.02.2014 20:26, Tomasz Figa wrote:
Hi Chris,
On 07.02.2014 10:58, Tomasz Figa wrote:
Hi Chris,
On 11.01.2014 22:39, Tomasz Figa wrote:
On platforms prior to Exynos the SDHCI block used internal clock
divider controlled by SELFREQ field of CLKCON register to divide base
clock selected
Hi,
On Mon, Mar 03 2014, Tomasz Figa wrote:
It's been almost two months since I posted this series, it's been
already ACKed and it would be nice to have it applied for upcoming
release.
Sorry about this, Tomasz -- now pushed to mmc-next for 3.15, thanks.
- Chris.
--
Chris Ball
On 03.03.2014 16:24, Chris Ball wrote:
Hi,
On Mon, Mar 03 2014, Tomasz Figa wrote:
It's been almost two months since I posted this series, it's been
already ACKed and it would be nice to have it applied for upcoming
release.
Sorry about this, Tomasz -- now pushed to mmc-next for 3.15,
Hi Chris,
On 07.02.2014 10:58, Tomasz Figa wrote:
Hi Chris,
On 11.01.2014 22:39, Tomasz Figa wrote:
On platforms prior to Exynos the SDHCI block used internal clock
divider controlled by SELFREQ field of CLKCON register to divide base
clock selected from several external clocks fed to the
Hi Chris,
On 11.01.2014 22:39, Tomasz Figa wrote:
On platforms prior to Exynos the SDHCI block used internal clock
divider controlled by SELFREQ field of CLKCON register to divide base
clock selected from several external clocks fed to the block by
SELBASECLK bitfield of CONTROL2 register.
Hi Jaehoon, Heiko,
On 13.01.2014 06:47, Jaehoon Chung wrote:
Hi, All.
On 01/13/2014 06:18 AM, Heiko Stübner wrote:
Am Samstag, 11. Januar 2014, 22:39:00 schrieb Tomasz Figa:
Tested on S3C6410-based Mini6410 board, with following performance
figures:
* Before this series (133 MHz HCLK always
Am Samstag, 11. Januar 2014, 22:39:00 schrieb Tomasz Figa:
Tested on S3C6410-based Mini6410 board, with following performance
figures:
* Before this series (133 MHz HCLK always selected, leading to at most
33 MHz card clock):
root@tiny6410:~# hdparm -t /dev/mmcblk0
/dev/mmcblk0:
Hi, All.
On 01/13/2014 06:18 AM, Heiko Stübner wrote:
Am Samstag, 11. Januar 2014, 22:39:00 schrieb Tomasz Figa:
Tested on S3C6410-based Mini6410 board, with following performance
figures:
* Before this series (133 MHz HCLK always selected, leading to at most
33 MHz card clock):
On platforms prior to Exynos the SDHCI block used internal clock
divider controlled by SELFREQ field of CLKCON register to divide base
clock selected from several external clocks fed to the block by
SELBASECLK bitfield of CONTROL2 register. Depending on wanted clock
frequency, different external
