>From 590eb2cc052330b7a4f68fb2df6255d65e249e1d Mon Sep 17 00:00:00 2001 From: Philip Rakity <prak...@marvell.com> Date: Mon, 20 Dec 2010 21:47:37 -0800 Subject: [PATCH] sdhci: support hardware clock gating in the SD layer
Define callback (platform_hw_clk_gate) that is called when H/W clock gating
is defined. The adaptation layer is responsible for enabling hw clock
gating by:
a) setting mmc->caps |= MMC_CAP_HW_CLOCK_GATING to enable h/w gating
b) defining the callback.
Signed-off-by: Philip Rakity <prak...@marvell.com>
Signed-off-by: Mark F. Brown <ma...@marvell.com>
Tested-by: Philip Rakity <prak...@marvell.com>
---
drivers/mmc/host/sdhci.c | 6 ++++++
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ff9d5f0..dcfbe83 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1203,6 +1203,12 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
if (host->ops->platform_send_init_74_clocks)
host->ops->platform_send_init_74_clocks(host, ios->power_mode);
+#ifdef CONFIG_MMC_CLKGATE
+ if ((mmc->caps & MMC_CAP_HW_CLOCK_GATING)
+ && host->ops->platform_hw_clk_gate)
+ host->ops->platform_hw_clk_gate(host);
+#endif
+
/*
* If your platform has 8-bit width support but is not a v3 controller,
* or if it requires special setup code, you should implement that in
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 84292e0..cbd63e2 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -241,6 +241,7 @@ struct sdhci_ops {
void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
unsigned int (*get_f_max_clock)(struct sdhci_host *host);
void (*platform_specific_delay)(struct sdhci_host *host);
+ void (*platform_hw_clk_gate)(struct sdhci_host *host);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
--
1.6.0.4
0020-sdhci-support-hardware-clock-gating-in-the-SD-layer.patch
Description: 0020-sdhci-support-hardware-clock-gating-in-the-SD-layer.patch
