On 4 November 2014 08:32, Vincent Wan wrote:
> SDHC controller in AMD chipsets require SDHC transfer mode
> register to be cleared for commands without data. The issue was
> uncovered during testing eMMC cards on KB/ML based platforms.
>
> Signed-off-by: Vincent Wan
> Signed-off-by: Arindam Nath
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms.
Signed-off-by: Vincent Wan
Signed-off-by: Arindam Nath
Cc: Huang Rui
Tested-by: Vikram B
Tested-by: Raghavend