Re: [PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

2014-11-04 Thread Ulf Hansson
On 4 November 2014 08:32, Vincent Wan wrote: > SDHC controller in AMD chipsets require SDHC transfer mode > register to be cleared for commands without data. The issue was > uncovered during testing eMMC cards on KB/ML based platforms. > > Signed-off-by: Vincent Wan > Signed-off-by: Arindam Nath

[PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

2014-11-04 Thread Vincent Wan
SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan Signed-off-by: Arindam Nath Cc: Huang Rui Tested-by: Vikram B Tested-by: Raghavend