On 28 January 2015 at 17:45, Rhyland Klein rkl...@nvidia.com wrote:
From: Pavan Kunapuli pkunap...@nvidia.com
If there is a gap between xfer mode and command register writes,
tegra SDMMC controller can sometimes issue a spurious command before
the CMD register is written. To avoid this, these
From: Pavan Kunapuli pkunap...@nvidia.com
If there is a gap between xfer mode and command register writes,
tegra SDMMC controller can sometimes issue a spurious command before
the CMD register is written. To avoid this, these two registers need
to be written together in a single write operation.
