Re: [PATCH v3 1/3] mmc:sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

On 5 November 2014 07:09, Vincent Wan wrote: > SDHC controller in AMD chipsets require SDHC transfer mode > register to be cleared for commands without data. The issue was > uncovered during testing eMMC cards on KB/ML based platforms > > Signed-off-by: Vincent Wan > Signed-off-by: Wan Zongshun

[PATCH v3 1/3] mmc:sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms Signed-off-by: Vincent Wan Signed-off-by: Wan Zongshun Signed-off-by: Arindam Nath Tested-by: Vikram B Tested-