On Friday, December 13, 2013, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> All implementations of the Synopsys DW SD/MMC IP have settings to control
> the phase shift of the CIU clk. These phase shift settings are necessary for
> the SD/MMC to correctly clock the card. All variants of the dw_mmc wi
On 16 December 2013 11:24, Dinh Nguyen wrote:
>
> @@ -2478,6 +2480,27 @@ int dw_mci_probe(struct dw_mci *host)
>dev_dbg(host->dev, "ciu clock not available\n");
>host->bus_hz = host->pdata->bus_hz;
>} else {
> +/* If the CIU clk is availa
On 12/14/13 10:37 PM, zhangfei wrote:
>
>
> On 12/15/2013 11:16 AM, Dinh Nguyen wrote:
>> Hi Zhangfei,
>>
@@ -2478,6 +2480,27 @@ int dw_mci_probe(struct dw_mci *host)
dev_dbg(host->dev, "ciu clock not available\n");
host->bus_hz = host->pdata->bus_hz;
On 12/15/2013 11:16 AM, Dinh Nguyen wrote:
Hi Zhangfei,
@@ -2478,6 +2480,27 @@ int dw_mci_probe(struct dw_mci *host)
dev_dbg(host->dev, "ciu clock not available\n");
host->bus_hz = host->pdata->bus_hz;
} else {
+/* If the CIU clk is available, we check for
Hi Zhangfei,
On 12/14/13 8:05 PM, zhangfei wrote:
> Dear Dinh
>
> On 12/13/2013 04:30 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> All implementations of the Synopsys DW SD/MMC IP have settings to
>> control
>> the phase shift of the CIU clk. These phase shift settings are
>> necessa
Dear Dinh
On 12/13/2013 04:30 AM, dingu...@altera.com wrote:
From: Dinh Nguyen
All implementations of the Synopsys DW SD/MMC IP have settings to control
the phase shift of the CIU clk. These phase shift settings are necessary for
the SD/MMC to correctly clock the card. All variants of the dw_m
From: Dinh Nguyen
All implementations of the Synopsys DW SD/MMC IP have settings to control
the phase shift of the CIU clk. These phase shift settings are necessary for
the SD/MMC to correctly clock the card. All variants of the dw_mmc will need
these settings, but how they are implemented can va
