Quoting Dinh Nguyen (2014-01-15 04:36:52)
Hi Mike,
Can you apply this to your clk tree?
The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
3.14-rc1?
Thanks,
Mike
Thanks,
Dinh
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On Wed, 2014-02-05 at 08:03 -0800, Mike Turquette wrote:
Quoting Dinh Nguyen (2014-01-15 04:36:52)
Hi Mike,
Can you apply this to your clk tree?
The patch looks good to me, but I think it depends on your pending pull
request. Can you add this to that pull request and rebase it to
Hi Mike,
On 1/9/14 9:47 PM, Jaehoon Chung wrote:
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
On 01/10/2014 06:31 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC
Hi Dinh,
On Fri, January 10, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's
Hi Seungwong,
On Fri, 2014-01-10 at 22:19 +0900, Seungwon Jeon wrote:
Hi Dinh,
On Fri, January 10, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare
On Friday 10 January 2014, Dinh Nguyen wrote:
diff --git a/arch/arm/boot/dts/socfpga.dtsi
b/arch/arm/boot/dts/socfpga.dtsi
index f936476..e776512 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -413,6 +413,7 @@
Hi Arnd,
On 1/10/14 1:00 PM, Arnd Bergmann wrote:
On Friday 10 January 2014, Dinh Nguyen wrote:
diff --git a/arch/arm/boot/dts/socfpga.dtsi
b/arch/arm/boot/dts/socfpga.dtsi
index f936476..e776512 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -413,6
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
On 01/10/2014 06:31 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
