On Mon, 2013-12-16 at 16:20 +0900, Seungwon Jeon wrote:
> On Mon, December 16, 2013, Dinh Nguyen wrote:
> > On 12/15/13 10:23 PM, Seungwon Jeon wrote:
> > > On Mon, December 09, 2013, Dinh Nguyen wrote:
> > >> From: Dinh Nguyen
> > >>
> > >> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit wh
On Mon, December 16, 2013, Dinh Nguyen wrote:
> On 12/15/13 10:23 PM, Seungwon Jeon wrote:
> > On Mon, December 09, 2013, Dinh Nguyen wrote:
> >> From: Dinh Nguyen
> >>
> >> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
> >> operating all timing modes, except for SDR50, DD
On 12/15/13 10:23 PM, Seungwon Jeon wrote:
> On Mon, December 09, 2013, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
>> operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
>>
>> According to the Synops
On Mon, December 09, 2013, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
> operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
>
> According to the Synopsys databook :"To meet the relatively high Input Ho
On Mon, 2013-12-09 at 10:56 +0100, Heiko Stübner wrote:
> Hi,
>
> Am Montag, 9. Dezember 2013, 05:51:06 schrieb dingu...@altera.com:
> > From: Dinh Nguyen
> >
> > This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
> > operating all timing modes, except for SDR50, DDR50, SDR10
Hi,
Am Montag, 9. Dezember 2013, 05:51:06 schrieb dingu...@altera.com:
> From: Dinh Nguyen
>
> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
> operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
>
> According to the Synopsys databook :"To meet th