Hi,
On Tue, Jan 24, 2012 at 16:46:05, Ido Yariv wrote:
The davinci mmc interrupt handler fills the fifo, as long as the DXRDY
or DRRDY bits are set in the status register.
If interrupts fire during this loop, they will be handled by the
handler, but the interrupt controller will still
Hello Sudhakar,
On Fri, Jan 27, 2012 at 08:11:55AM +, Rajashekhara, Sudhakar wrote:
I tested both these patches and they work fine on the OMAP-L138 EVM. I
observed that with these patches the number of interrupts during a transfer
are less compared to earlier. For a 100 MB transfer, I
Hello Ido,
On Tue, Jan 24, 2012 at 16:46:05, Ido Yariv wrote:
The davinci mmc interrupt handler fills the fifo, as long as the DXRDY
or DRRDY bits are set in the status register.
If interrupts fire during this loop, they will be handled by the
handler, but the interrupt controller will
