IIUC this series is about devdax namespace with aligh of 1G or 2M where we can
save the vmmemap space by not allocating memory for tail struct pages?
Dan Williams writes:
> > enum:
>> >
>> > enum devmap_geometry {
>> > DEVMAP_PTE,
>> > DEVMAP_PMD,
>> > DEVMAP_PUD,
>> > }
>> >
>>
Vaibhav Jain writes:
> In case performance stats for an nvdimm are not available, reading the
> 'perf_stats' sysfs file returns an -ENOENT error. A better approach is
> to make the 'perf_stats' file entirely invisible to indicate that
> performance stats for an nvdimm are unavailable.
>
> So this
On 5/4/21 11:13 AM, Pankaj Gupta wrote:
What this patch series did was to express that property via a device
tree node and guest driver enables a hypercall based flush mechanism to
ensure persistence.
Would VIRTIO (entirely asynchronous, no trap at host side) based
mechanism is better
th
On 5/4/21 1:11 AM, Dan Williams wrote:
On Mon, May 3, 2021 at 7:06 AM Shivaprasad G Bhat wrote:
.
The proposal that "sync-dax=unsafe" for non-PPC architectures, is a
fundamental misrepresentation of how this is supposed to work. Rather
than make "sync-dax" a first class citizen of th
On 5/1/21 12:44 AM, Dan Williams wrote:
Some corrections to terminology confusion below...
...
file on the host in case of file backed v-nvdimms. This is addressed by
virtio-pmem in case of x86_64 by making explicit flushes translating to
fsync at qemu.
Note that virtio-pmem was a pro
On 4/29/21 9:25 PM, Stefan Hajnoczi wrote:
On Wed, Apr 28, 2021 at 11:48:21PM -0400, Shivaprasad G Bhat wrote:
The nvdimm devices are expected to ensure write persistence during power
failure kind of scenarios.
The libpmem has architecture specific instructions like dcbf on POWER
to flush the c
Vaibhav Jain writes:
> Hi Shiva,
>
> Apologies for a late review but something just caught my eye while
> working on a different patch.
>
> Shivaprasad G Bhat writes:
>
>> Add support for ND_REGION_ASYNC capability if the device tree
>> indicates 'ibm,hcall-flush-required' property in the NVDIMM
x27; without any explicit mappings as in case of
> virtio-pmem.
>
> References:
> [1] "powerpc/papr_scm: Implement support for H_SCM_FLUSH hcall"
> https://lore.kernel.org/linux-nvdimm/161703936121.36.7260632399582101498.stgit@e1fbed493c87
>
Reviewed-by: Aneesh
On 4/6/21 5:07 PM, Vaibhav Jain wrote:
Hi Aneesh,
Thanks for looking into this patch.
"Aneesh Kumar K.V" writes:
Vaibhav Jain writes:
In case a platform doesn't provide explicit flush-hints but provides an
explicit flush callback via ND_REGION_ASYNC region flag, then
n
Vaibhav Jain writes:
> In case a platform doesn't provide explicit flush-hints but provides an
> explicit flush callback via ND_REGION_ASYNC region flag, then
> nvdimm_has_flush() still returns '0' indicating that writes do not
> require flushing. This happens on PPC64 with patch at [1] applied,
Santosh Sivaraj writes:
> For NFIT to be available ACPI is a must, so don't fail when nfit modules
> are missing on a platform that doesn't support ACPI.
>
> Signed-off-by: Santosh Sivaraj
> ---
> test.h| 2 +-
> test/ack-shutdown-count-set.c | 2 +-
> test/blk_namespa
Vaibhav Jain writes:
> In case a platform doesn't provide explicit flush-hints but provides an
> explicit flush callback via ND_REGION_ASYNC region flag, then
> nvdimm_has_flush() still returns '0' indicating that writes do not
> require flushing. This happens on PPC64 with patch at [1] applied,
On 3/31/21 3:50 PM, Michael Ellerman wrote:
"Aneesh Kumar K.V" writes:
Shivaprasad G Bhat writes:
Add support for ND_REGION_ASYNC capability if the device tree
indicates 'ibm,hcall-flush-required' property in the NVDIMM node.
Flush is done by issuing H_SCM_FLUSH hcall to
Tyler Hicks writes:
> The alignment constraint for namespace creation in a region was
> increased, from 2M to 16M, for non-PowerPC architectures in v5.7 with
> commit 2522afb86a8c ("libnvdimm/region: Introduce an 'align'
> attribute"). The thought behind the change was that region alignment
> sho
gt;
> The patch updates papr_scm_nvdimm_init() to force query of nvdimm
> health via __drc_pmem_query_health() and if nvdimm is found to be
> unarmed then set the nvdimm flag ND_UNARMED for nvdimm_create().
>
Reviewed-by: Aneesh Kumar K.V
> Signed-off-by: Vaibhav Jain
> ---
tests/blob/master/memory/ndctl.py.data/map_sync.c
Reviewed-by: Aneesh Kumar K.V
>
> Signed-off-by: Shivaprasad G Bhat
> ---
> v2 - https://www.spinics.net/lists/kvm-ppc/msg18799.html
> Changes from v2:
>- Fixed the commit message.
>- Add dev_dbg before the H_S
On 3/24/21 8:39 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 09:47:55AM -0400, Shivaprasad G Bhat wrote:
The patch adds the 'sync-dax' property to the nvdimm device.
When the sync-dax is 'off', the device tree property
"hcall-flush-required" is added to the nvdimm node which makes the
guest
On 3/24/21 8:37 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 09:47:38AM -0400, Shivaprasad G Bhat wrote:
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch.
The hcall expects the semantics such that the flus
-user disabled THP
via sysfs file (/sys/kernel/mm/transparent_hugepage/enabled). Hence
differentiate between hardware/firmware lacking support vs user-controlled
disable of THP and prevent a huge fault if the hardware lacks hugepage
support.
Signed-off-by: Aneesh Kumar K.V
---
include/li
On 12/8/20 3:30 AM, Dan Williams wrote:
On Mon, Oct 5, 2020 at 6:01 PM Santosh Sivaraj wrote:
...
+static int ndtest_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
+ void *iobuf, u64 len, int rw)
+{
+ struct ndtest_dimm *dimm = ndbr->blk_provider_data;
+
On 12/1/20 6:17 PM, Pankaj Gupta wrote:
Tha patch implements SCM async-flush hcall and sets the
ND_REGION_ASYNC capability when the platform device tree
has "ibm,async-flush-required" set.
So, you are reusing the existing ND_REGION_ASYNC flag for the
hypercall based async flush with device tree
Hi All,
"Aneesh Kumar K.V" writes:
> On power platforms we can find
> # cat /sys/devices/system/memory/memory0/phys_index
>
>
> This results in
>
> libdaxctl: memblock_in_dev: dax1.0: memory0: Unable to determine phys_index:
> Success
>
> Av
On 10/23/20 12:40 AM, Ira Weiny wrote:
On Thu, Oct 22, 2020 at 11:19:43AM -0700, Ralph Campbell wrote:
On 10/22/20 8:41 AM, Ira Weiny wrote:
On Thu, Oct 22, 2020 at 11:37:53AM +0530, Aneesh Kumar K.V wrote:
commit 6f42193fd86e ("memremap: don't use a separate devm
rite+0x84/0x140
[c00025c1fd80] [c003a430] system_call_exception+0x120/0x270
[c00025c1fe20] [c000c540] system_call_common+0xf0/0x27c
Cc: Christoph Hellwig
Cc: Dan Williams
Cc: Sachin Sant
Cc: linux-nvdimm@lists.01.org
Cc: Ira Weiny
Cc: Jason Gunthorpe
Signed-off-by: Aneesh Kum
"Aneesh Kumar K.V" writes:
> Hi Christoph,
>
> commit 6f42193fd86e ("memremap: don't use a separate devm action for
> devmap_managed_enable_get") changed the static key updates such that we
> are now calling devmap_managed_e
Hi Christoph,
commit 6f42193fd86e ("memremap: don't use a separate devm action for
devmap_managed_enable_get") changed the static key updates such that we
are now calling devmap_managed_enable_put() without doing the equivalent
devmap_managed_enable_get().
devmap_managed_enable_get() is only ca
On power platforms we can find
# cat /sys/devices/system/memory/memory0/phys_index
This results in
libdaxctl: memblock_in_dev: dax1.0: memory0: Unable to determine phys_index:
Success
Avoid considering phys_index == 0 as error.
Signed-off-by: Aneesh Kumar K.V
---
daxctl/lib
rmance
statistics.
Fixes: 2d02bf835e573 ('powerpc/papr_scm: Fetch nvdimm performance stats from
PHYP')
Reported-by: Aneesh Kumar K.V
Signed-off-by: Vaibhav Jain
---
arch/powerpc/platforms/pseries/papr_scm.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/platforms
t buffer
> large enough to hold the performance stat and passes it to
> drc_pmem_query_stats() that issues the HCALL to PHYP. The return value
> of the stat is then populated in the 'struct
> nd_papr_pdsm_health.dimm_fuel_gauge' field with extension flag
> 'PDSM_DIMM_HEALTH
Vaibhav Jain writes:
> Update papr_scm.c to query dimm performance statistics from PHYP via
> H_SCM_PERFORMANCE_STATS hcall and export them to user-space as PAPR
> specific NVDIMM attribute 'perf_stats' in sysfs. The patch also
> provide a sysfs ABI documentation for the stats being reported and
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/lib/pmem.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc
subsequent instructions is initiated.
This is in addition to the ordering done by wmb()
Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.
Reviewed-by: Dan Williams
Signed-off-by: Aneesh Kumar
pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/barrier.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/powerpc
"pmem-region-v2"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/papr_scm.c | 1 +
drivers/nvdimm/of_pmem.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.
.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 1 +
arch/powerpc/lib/pmem.c | 50 ---
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h
b/arch/powerpc/include/asm/cacheflush.h
index
ant to add ppc64 specific cpu feature check in of_pmem driver.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/pmem.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/pmem.c
b/arch/powerpc/platforms/pseries/pmem.c
index f860a897a9e0..23
x27;t differentiate.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/ppc-opcode.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..1ad014e4633e 100644
--- a/arch/powerpc/includ
and related changes
Changes from V4:
* Add namespace specific sychronous fault control.
Changes from V3:
* Add new compat string to be used for the device.
* Use arch_pmem_flush_barrier() in dm-writecache.
Aneesh Kumar K.V (7):
powerpc/pmem: Restrict papr_scm to P8 and above.
powerpc/pmem: Add
On 7/1/20 1:15 AM, Dan Williams wrote:
On Tue, Jun 30, 2020 at 2:21 AM Aneesh Kumar K.V
wrote:
[..]
The bio argument isn't for range based flushing, it is for flush
operations that need to complete asynchronously.
How does the block layer determine that the pmem device needs
asynchr
Update patch.
>From 1e6aa6c4182e14ec5d6bf878ae44c3f69ebff745 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V"
Date: Tue, 12 May 2020 20:58:33 +0530
Subject: [PATCH] libnvdimm/nvdimm/flush: Allow architecture to override the
flush barrier
Architectures like ppc64 provide pers
On 6/30/20 2:24 PM, Michal Suchánek wrote:
On Mon, Jun 29, 2020 at 06:50:15PM -0700, Dan Williams wrote:
On Mon, Jun 29, 2020 at 1:41 PM Aneesh Kumar K.V
wrote:
Michal Suchánek writes:
Hello,
On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote:
nvdimm expect the flush
On 6/30/20 12:52 PM, Aneesh Kumar K.V wrote:
On 6/30/20 12:36 PM, Dan Williams wrote:
On Mon, Jun 29, 2020 at 10:02 PM Aneesh Kumar K.V
wrote:
Dan Williams writes:
On Mon, Jun 29, 2020 at 1:29 PM Aneesh Kumar K.V
wrote:
Architectures like ppc64 provide persistent memory specific
On 6/30/20 12:36 PM, Dan Williams wrote:
On Mon, Jun 29, 2020 at 10:02 PM Aneesh Kumar K.V
wrote:
Dan Williams writes:
On Mon, Jun 29, 2020 at 1:29 PM Aneesh Kumar K.V
wrote:
Architectures like ppc64 provide persistent memory specific barriers
that will ensure that all stores for which
Dan Williams writes:
> On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
> wrote:
>>
>> We only support persistent memory on P8 and above. This is enforced by the
>> firmware and further checked on virtualzied platform during platform init.
>> Add WARN_ONCE in pm
Dan Williams writes:
> On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
> wrote:
>>
>> of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
>> all previous writes are architecturally visible for the platform
>> buffer flush.
>>
>> Signed
Dan Williams writes:
> On Mon, Jun 29, 2020 at 1:29 PM Aneesh Kumar K.V
> wrote:
>>
>> Architectures like ppc64 provide persistent memory specific barriers
>> that will ensure that all stores for which the modifications are
>> written to persistent storage b
Michal Suchánek writes:
> Hello,
>
> On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote:
>> nvdimm expect the flush routines to just mark the cache clean. The barrier
>> that mark the store globally visible is done in nvdimm_flush().
>>
>>
subsequent instructions is initiated.
This is in addition to the ordering done by wmb()
Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
drivers/md/dm
kernel test robot writes:
> Hi "Aneesh,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on linux-nvdimm/libnvdimm-for-next v5.8-rc3
> next-20200629]
> [cannot apply to scottwood/next]
> [If your patch is applied to the wrong g
"pmem-region-v2"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/papr_scm.c | 1 +
drivers/nvdimm/of_pmem.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.
or the device.
* Use arch_pmem_flush_barrier() in dm-writecache.
Aneesh Kumar K.V (8):
powerpc/pmem: Restrict papr_scm to P8 and above.
powerpc/pmem: Add new instructions for persistent storage and sync
powerpc/pmem: Add flush routines using new pmem store and sync
instruction
libnvdimm/nvdimm/flush: A
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Update the papr_scm driver to a simplified nvdim_flush callback that do
only the required barrier.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/lib
.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 1 +
arch/powerpc/lib/pmem.c | 50 ---
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h
b/arch/powerpc/include/asm/cacheflush.h
index
subsequent instructions is initiated.
This is in addition to the ordering done by wmb()
Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
drivers/md/dm
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc
We only support persistent memory on P8 and above. This is enforced by the
firmware and further checked on virtualzied platform during platform init.
Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h
ant to add ppc64 specific cpu feature check in of_pmem driver.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/pmem.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/pmem.c
b/arch/powerpc/platforms/pseries/pmem.c
index f860a897a9e0..23
x27;t differentiate.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/ppc-opcode.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..1ad014e4633e 100644
--- a/arch/powerpc/includ
Aneesh Kumar K.V writes:
> Vaibhav Jain writes:
> + */
>> +seq_buf_init(&s, buf, PAGE_SIZE);
>> +for (index = 0, stat = stats->scm_statistic;
>> + index < stats->num_statistics; ++index, ++stat) {
>
Vaibhav Jain writes:
> Update papr_scm.c to query dimm performance statistics from PHYP via
> H_SCM_PERFORMANCE_STATS hcall and export them to user-space as PAPR
> specific NVDIMM attribute 'perf_stats' in sysfs. The patch also
> provide a sysfs ABI documentation for the stats being reported and
"Aneesh Kumar K.V" writes:
> This patch series enables the usage os new pmem flush and sync instructions
> on POWER
> architecture. POWER10 introduces two new variants of dcbf instructions
> (dcbstps and dcbfps)
> that can be used to write modified locations b
ant to add ppc64 specific cpu feature check in of_pmem driver.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/pmem.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/pmem.c
b/arch/powerpc/platforms/pseries/pmem.c
index f860a897a9e0..23
subsequent instructions is initiated.
This is in addition to the ordering done by wmb()
Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
drivers/md/dm
"pmem-region-v2"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/papr_scm.c | 1 +
drivers/nvdimm/of_pmem.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.
AP_SYNC_DISABLE=n
on ppc64 when we are confident that everybody is using the new flush
instruction.
Chaanges from V4:
* Add namespace specific sychronous fault control.
Changes from V3:
* Add new compat string to be used for the device.
* Use arch_pmem_flush_barrier() in dm-writecache.
We only support persistent memory on P8 and above. This is enforced by the
firmware and further checked on virtualzied platform during platform init.
Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc
.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 1 +
arch/powerpc/lib/pmem.c | 50 ---
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h
b/arch/powerpc/include/asm/cacheflush.h
index
t;ibm,pmemory-v2"
will disable the sync fault feature.
Signed-off-by: Aneesh Kumar K.V
---
drivers/dax/bus.c| 2 +-
drivers/dax/super.c | 73
drivers/nvdimm/pmem.c| 4 ++
drivers/nvdimm/region_devs.c | 16
include/l
x27;t differentiate.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/ppc-opcode.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..1ad014e4633e 100644
--- a/arch/powerpc/includ
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Update the papr_scm driver to a simplified nvdim_flush callback that do
only the required barrier.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/lib
allows user to control whether MAP_SYNC should be enabled by
default or not.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/Kconfig.cputype| 9 +
arch/powerpc/platforms/pseries/papr_scm.c | 17 -
drivers/nvdimm/of_pmem.c | 7 +++
3 files
"Aneesh Kumar K.V" writes:
> On 6/3/20 1:56 PM, Jan Kara wrote:
>> On Tue 02-06-20 17:59:08, Williams, Dan J wrote:
>>> [ forgive formatting, a series of unfortunate events has me using Outlook
>>> for the moment ]
>>>
>>>> From
On 6/3/20 1:56 PM, Jan Kara wrote:
On Tue 02-06-20 17:59:08, Williams, Dan J wrote:
[ forgive formatting, a series of unfortunate events has me using Outlook for
the moment ]
From: Jan Kara
These flags are device properties that affect the kernel and
userspace's handling of persistence.
"Aneesh Kumar K.V" writes:
> On 6/1/20 5:37 PM, Michal Suchánek wrote:
>> On Mon, Jun 01, 2020 at 05:31:50PM +0530, Aneesh Kumar K.V wrote:
>>> On 6/1/20 3:39 PM, Jan Kara wrote:
>>>> On Fri 29-05-20 16:25:35, Aneesh Kumar K.V wrote:
>>>>>
allows user to control whether MAP_SYNC should be enabled by
default or not.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/Kconfig.cputype | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/papr_scm.c | 17 -
drivers/nvdimm/of_pmem.c | 7 +++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries
disabled it for the namespace.
Signed-off-by: Aneesh Kumar K.V
---
include/linux/dax.h| 5 +++--
include/linux/sched/coredump.h | 13 ++---
include/uapi/linux/prctl.h | 3 +++
kernel/fork.c | 8 +++-
kernel/sys.c | 18
can be used to control this flag. If the device supports synchronous flush
then userspace can update this attribute to enable/disable the synchronous
fault. The attribute is only visible if there is write cache enabled on the
device.
Signed-off-by: Aneesh Kumar K.V
---
drivers/dax/super.c | 73
This patch makes sync fault enable/disable feature more fine-grained
by allowing region-wise control of the same.
In a followup patch on ppc64 only device with compat string "ibm,pmemory-v2"
will disable the sync fault feature.
Signed-off-by: Aneesh Kumar K.V
---
drivers
On 6/1/20 5:37 PM, Michal Suchánek wrote:
On Mon, Jun 01, 2020 at 05:31:50PM +0530, Aneesh Kumar K.V wrote:
On 6/1/20 3:39 PM, Jan Kara wrote:
On Fri 29-05-20 16:25:35, Aneesh Kumar K.V wrote:
On 5/29/20 3:22 PM, Jan Kara wrote:
On Fri 29-05-20 15:07:31, Aneesh Kumar K.V wrote:
Thanks
On 6/1/20 3:39 PM, Jan Kara wrote:
On Fri 29-05-20 16:25:35, Aneesh Kumar K.V wrote:
On 5/29/20 3:22 PM, Jan Kara wrote:
On Fri 29-05-20 15:07:31, Aneesh Kumar K.V wrote:
Thanks Michal. I also missed Jeff in this email thread.
And I think you'll also need some of the sched maintainer
On 5/30/20 12:52 AM, Dan Williams wrote:
On Fri, May 29, 2020 at 3:55 AM Aneesh Kumar K.V
wrote:
On 5/29/20 3:22 PM, Jan Kara wrote:
Hi!
On Fri 29-05-20 15:07:31, Aneesh Kumar K.V wrote:
Thanks Michal. I also missed Jeff in this email thread.
And I think you'll also need some o
On 5/29/20 3:22 PM, Jan Kara wrote:
Hi!
On Fri 29-05-20 15:07:31, Aneesh Kumar K.V wrote:
Thanks Michal. I also missed Jeff in this email thread.
And I think you'll also need some of the sched maintainers for the prctl
bits...
On 5/29/20 3:03 PM, Michal Suchánek wrote:
Adding Jan
O
Hi,
Thanks Michal. I also missed Jeff in this email thread.
-aneesh
On 5/29/20 3:03 PM, Michal Suchánek wrote:
Adding Jan
On Fri, May 29, 2020 at 11:11:39AM +0530, Aneesh Kumar K.V wrote:
With POWER10, architecture is adding new pmem flush and sync instructions.
The kernel should prevent
kernel config option is added to allow the user
to control whether MAP_SYNC should be enabled by default or not.
Signed-off-by: Aneesh Kumar K.V
---
include/linux/sched/coredump.h | 13 ++---
include/uapi/linux/prctl.h | 3 +++
kernel/fork.c | 8 +++-
kernel/sys.c
allows user to control whether MAP_SYNC should be enabled by
default or not.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/Kconfig.cputype | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index
"pmem-region-v2"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/papr_scm.c | 1 +
drivers/nvdimm/of_pmem.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.
We only support persistent memory on P8 and above. This is enforced by the
firmware and further checked on virtualzied platform during platform init.
Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h
.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/lib/pmem.c | 50 +
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 0666a8d29596..5a61aaeb6930 100644
--- a/arch/powerpc/lib/pmem.c
+++ b/arch
V3:
* Add new compat string to be used for the device.
* Use arch_pmem_flush_barrier() in dm-writecache.
Aneesh Kumar K.V (8):
powerpc/pmem: Restrict papr_scm to P8 and above.
powerpc/pmem: Add new instructions for persistent storage and sync
powerpc/pmem: Add flush routines using new pmem
subsequent instructions is initiated.
This is in addition to the ordering done by wmb()
Update nvdimm core such that architecture can use barriers other than
wmb to ensure all previous writes are architecturally visible for
the platform buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
drivers/md/dm
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Update the papr_scm driver to a simplified nvdim_flush callback that do
only the required barrier.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/lib
ant to add ppc64 specific cpu feature check in of_pmem driver.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/pmem.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/pmem.c
b/arch/powerpc/platforms/pseries/pmem.c
index f860a897a9e0..23
x27;t differentiate.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/ppc-opcode.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..1ad014e4633e 100644
--- a/arch/powerpc/includ
27;struct papr_scm_priv.health'
> thats an instance of 'struct nd_papr_pdsm_health' to cache the health
> information of a nvdimm. As a result functions drc_pmem_query_health()
> and flags_show() are updated to populate and use this new struct
> instead of a u64 integer t
and performs sanity tests on them. A new function
> papr_scm_service_pdsm() is introduced and is called from
> papr_scm_ndctl() in case of a PDSM request is received via ND_CMD_CALL
> command from libnvdimm.
>
Reviewed-by: Aneesh Kumar K.V
> Cc: "Aneesh Kumar K . V"
>
y
> the the new sysfs attribute 'papr/flags' is also introduced at
> Documentation/ABI/testing/sysfs-bus-papr-scm.
>
> [1] commit 58b278f568f0 ("powerpc: Provide initial documentation for
> PAPR hcalls")
>
Reviewed-by: Aneesh Kumar K.V
> Cc: "Anee
On 5/22/20 3:01 PM, Michal Suchánek wrote:
On Thu, May 21, 2020 at 02:52:30PM -0400, Mikulas Patocka wrote:
On Thu, 21 May 2020, Dan Williams wrote:
On Thu, May 21, 2020 at 10:03 AM Aneesh Kumar K.V
wrote:
Moving on to the patch itself--Aneesh, have you audited other persistent
memory
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