Paul,
On Thursday 08 September 2011 10:51 AM, Santosh Shilimkar wrote:
The series contains few fixes and clean-up for OMAP.
Briefly,
- HWMOD fix for the address space count
- Improving the L3 register accesses
- Bug fix in the L3 error handler
- Sparce warning and indentation fixes in L3
The series adds OMAP4 MPUSS (MPU SubSystem) power management support for
suspend (S2R), CPU hotplug and CPUidle.
This is a repost with minor changelog updates, re-basing against 3.1-rc6,
adding reiwed-by/tested-by etc and re-ordering of errata patch.
The main change is the errata i688 is cleanly
OMAP4 L2X0 initialisation code uses BUG_ON() for the ioremap()
failure scenarios.
Use WARN_ON() instead and allow graceful function exits.
This was suggsted by Kevin Hilman khil...@ti.com during
OMAP4 PM code review.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet
This patch adds SAR RAM support on OMAP4430. SAR RAM used to save
and restore the HW context in low power modes.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
---
This patch exports APIs to get base address for GIC
distributor, CPU interface, SCU and PL310 L2 Cache which
are used in OMAP4 PM code.
This was suggested by Kevin Hilman khil...@ti.com during
OMAP4 PM code review.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet
On OMAP4430 ES1.0, Power Management features are not supported.
Avoid omap4_pm_init() on ES1.0 silicon so that we can continue
to use same kernel binary to boot on all OMAP4 silicons.
The ES1.0 boot failure with OMAP4 PM series was because of
the clockdomain initialisation code. Hardware
As per OMAP4430 TRM, the dynamic dependency between MPUSS - EMIF
and MPUSS - L4PER/L3_* and DUCATI - L3_* clockdomains is enable
by default. Refer register CM_MPU_DYNAMICDEP description for details.
But these dynamic dependencies doesn't work as expected. The hardware
recommendation is to enable
Initialise hardware supervised mode for all clockdomains if it's
supported. Initiate sleep transition for other clockdomains,
if they are not being used.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Allocate the memory to save secure ram context which needs
to be done when MPU is hitting OFF mode.
The ROM code expects a physical address to this memory
and hence use memblock APIs to reserve this memory as part
of .reserve() callback. Maximum size as per secure RAM requirements
is allocated.
Remove the __INIT from omap_secondary_startup() so that it can
be re-used for CPU hotplug.
While at this, remove the un-used AUXBOOT register reference.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Default arch_idle() isn't good enough for OMAP4 because of aync bridge errata
and necessity of NOPs post WFI to avoid speculative prefetch aborts.
Hence Use OMAP4 custom omap_do_wfi() hook for default idle.
Later in the series, async bridge errata work-around patch updates the
omap_do_wfi() with
With OMAP4 suspend, idle and hotplug series, we no longer need
do_wfi() macro.
Remove the same.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
---
The SGI(Software Generated Interrupts) are not wakeup capable from
low power states. This is known limitation on OMAP4 and needs to be
worked around by using software forced clockdomain wake-up. CPU0 forces
the CPU1 clockdomain to software force wakeup.
More details can be found in OMAP4430 TRM -
Program non-boot CPUs to hit lowest supported power state
when it is off-lined using cpu hotplug framework.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
---
OMAP WakeupGen is the interrupt controller extension used along
with ARM GIC to wake the CPU out from low power states on
external interrupts.
The WakeupGen unit is responsible for generating the wakeup event
from the incoming interrupts and enable bits. It is implemented
in the MPU always ON
Add WakeupGen and secure GIC low power support to save and restore
it's registers. WakeupGen Registers are saved to pre-defined SAR RAM layout
and the restore is automatically done by hardware(ROM code) while coming
out of MPUSS OSWR or Device off state. Secure GIC is saved using secure
API and
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
retention (CSWR) is not supported by hardware design.
The CPUx OFF mode isn't supported on OMAP4430 ES1.0
CPUx sleep code is common for hotplug, suspend and CPUilde.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff
Add OMAP4 CPUIDLE support. CPU1 is left with defualt idle and
the low power state for it is managed via cpu-hotplug.
This patch adds MPUSS low power states in cpuidle.
C1 - CPU0 ON + CPU1 ON + MPU ON
C2 - CPU0 OFF + CPU1 OFF + MPU CSWR
C3 - CPU0 OFF + CPU1 OFF + MPU OSWR
When MPUSS hits off-mode, L2 cache is lost. This patch adds L2X0
necessary maintenance operations and context restoration in the
low power code.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Jean Pihet j-pi...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Tested-by:
CPU local timer(TWD) stops when the CPU is transitioning into
deeper C-States. Since these timers are not wakeup capable, we
need the wakeup capable global timer to program the wakeup time
depending on the next timer expiry.
It can be handled by registering a global wakeup capable timer along
Save VFP CPU context using CPU PM notifier chain. VFP context
is lost when CPU hits OFF state.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Kevin Hilman khil...@ti.com
Tested-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 15
This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
OSWR configuration is as below.
- CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained
OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
anymore just like CORE power domain. The
On OMAP4 SOC, intecronnects has many write buffers in the async bridges
and they need to be drained before CPU enters into standby state.
Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support
but OMAP errata i688 (Async Bridge Corruption) needs to be taken
care to avoid issues like
This patch adds MPUSS(MPU Sub System) power domain
CSWR(Close Switch Retention) support to system wide suspend.
For MPUSS power domain to hit retention(CSWR or OSWR), both
CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
since CPU power domain CSWR is not supported by hardware
On OMAP secure/emulation devices, certain APIs are exported by secure
code. Add an infrastructure so that relevant operations on secure
devices can be implemented using it.
While at this, rename omap44xx-smc.S to omap-smc.S since the common APIs
can be used on other OMAP's too.
Signed-off-by:
Hi
On Fri, 23 Sep 2011, Munegowda, Keshava wrote:
Paul Walmsley p...@pwsan.com wrote:
So I'd suggest one of two approaches:
1. If the pin muxing can follow the PM runtime status of the UHH IP block,
then the pin mux data should be associated with the UHH hwmod.
No, the mux is
On Fri, 23 Sep 2011, Munegowda, Keshava wrote:
On Thu, Sep 22, 2011 at 11:31 PM, Paul Walmsley p...@pwsan.com wrote:
But the question arises here , why do we need these ehci and ohci as two
different hwmods containing only irq and base address? It is required
for future - to implement
Hi Santosh
On Sat, 24 Sep 2011, Santosh Shilimkar wrote:
On Thursday 08 September 2011 10:51 AM, Santosh Shilimkar wrote:
The series contains few fixes and clean-up for OMAP.
Briefly,
- HWMOD fix for the address space count
- Improving the L3 register accesses
- Bug fix in the L3
On Saturday 24 September 2011 12:01 PM, Paul Walmsley wrote:
Hi Santosh
On Sat, 24 Sep 2011, Santosh Shilimkar wrote:
On Thursday 08 September 2011 10:51 AM, Santosh Shilimkar wrote:
The series contains few fixes and clean-up for OMAP.
Briefly,
- HWMOD fix for the address space count
-
On Fri, 23 Sep 2011, Munegowda, Keshava wrote:
On Thu, Sep 22, 2011 at 11:31 PM, Paul Walmsley p...@pwsan.com wrote:
On Thu, 22 Sep 2011, Keshava Munegowda wrote:
4. usb_tll_hs hwmod of usbhs with the TLL base address and irq.
Signed-off-by: Keshava Munegowda keshava_mgo...@ti.com
Hi
On Sat, 24 Sep 2011, Santosh Shilimkar wrote:
On Saturday 24 September 2011 12:01 PM, Paul Walmsley wrote:
Hi Santosh
On Sat, 24 Sep 2011, Santosh Shilimkar wrote:
On Thursday 08 September 2011 10:51 AM, Santosh Shilimkar wrote:
I need your ack on below two patches so that I
On Fri, 23 Sep 2011, J, KEERTHY wrote:
On Fri, Sep 23, 2011 at 11:28 AM, Paul Walmsley p...@pwsan.com wrote:
On Fri, 23 Sep 2011, J, KEERTHY wrote:
On Fri, Sep 23, 2011 at 10:48 AM, Paul Walmsley p...@pwsan.com wrote:
On Thu, 22 Sep 2011, Keerthy wrote:
---
On Saturday 24 September 2011 01:06 PM, Paul Walmsley wrote:
Hi
On Sat, 24 Sep 2011, Santosh Shilimkar wrote:
On Saturday 24 September 2011 12:01 PM, Paul Walmsley wrote:
Hi Santosh
On Sat, 24 Sep 2011, Santosh Shilimkar wrote:
On Thursday 08 September 2011 10:51 AM, Santosh Shilimkar
On Fri, 23 Sep 2011, J, KEERTHY wrote:
On Fri, Sep 23, 2011 at 11:33 AM, Paul Walmsley p...@pwsan.com wrote:
On Thu, 22 Sep 2011, Keerthy wrote:
@@ -0,0 +1,175 @@
+/*
+ * OMAP system control module header file
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated -
Paul,
On Sunday 18 September 2011 02:28 PM, Santosh wrote:
On Friday 16 September 2011 09:10 PM, Cousson, Benoit wrote:
Hi Sricharan,
On 9/9/2011 6:02 PM, R, Sricharan wrote:
The address spaces, irqs and dma reqs count API returns the
number of corresponding entries in a hwmod including a
On Fri, 23 Sep 2011, J, KEERTHY wrote:
On Fri, Sep 23, 2011 at 11:33 AM, Paul Walmsley p...@pwsan.com wrote:
On Thu, 22 Sep 2011, Keerthy wrote:
diff --git a/arch/arm/mach-omap2/temp_sensor4460_data.c
b/arch/arm/mach-omap2/temp_sensor4460_data.c
new file mode 100644
index
Tony,
Please pull few OMAP sparse/bug fixes and clean-up for 3.2
Thnaks,
Santosh
The following changes since commit b6fd41e29dea9c6753b1843a77e50433e6123bcb:
Linux 3.1-rc6 (2011-09-12 14:02:02 -0700)
are available in the git repository at:
On Saturday 24 September 2011 09:26 AM, DebBarma, Tarun Kanti wrote:
[...]
After debugging this myself a bit, here's what I think may be going on.
This may not be the only problem but here's at least one of them.
First, debounce clocks are disabled in the runtime_suspend callback.
When a
On Sat, Sep 24, 2011 at 1:29 PM, Paul Walmsley p...@pwsan.com wrote:
On Fri, 23 Sep 2011, J, KEERTHY wrote:
On Fri, Sep 23, 2011 at 11:33 AM, Paul Walmsley p...@pwsan.com wrote:
On Thu, 22 Sep 2011, Keerthy wrote:
diff --git a/arch/arm/mach-omap2/temp_sensor4460_data.c
Santosh, Kevin,
[...]
After that, pm_runtime_put_sync() is called, which will trigger the
driver's -runtime_suspend callback. The -runtime_suspend() callback
checks bank-mod_usage as well, and if zero, doesn't do anything
(notably, it doesn't disable debounce clocks.)
I need some
On Tue, Mar 29, 2011 at 8:32 AM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
I think that Sakari's patches correcty fix the problems he noticed. However,
they won't fix one basic issue, which is that the iommu2 module won't be
automatically pulled in when the omap3isp module is
On Fri, Sep 16, 2011 at 08:51:43PM +0300, Ohad Ben-Cohen wrote:
Let the IOMMU core know we support 4KiB, 64KiB, 1MiB and 16MiB page sizes.
This way the IOMMU core can split any arbitrary-sized physically
contiguous regions (that it needs to map) as needed.
Signed-off-by: Ohad Ben-Cohen
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