On Tue, Jan 31, 2012 at 12:12:20AM +0100, Víctor Manuel Jáquez Leal wrote:
Silence the warning when compiling drv_interface.c
Signed-off-by: Víctor Manuel Jáquez Leal vjaq...@igalia.com
What does the compiler warn about here? Normally you would cut and
paste the warning into the commit
Hi Kevin and Paul,
On 1/31/2012 12:14 AM, Kevin Hilman wrote:
Hi Paul,
Paul Walmsleyp...@pwsan.com writes:
This series does some cleanup and documentation on the OMAP hwmod code
(and a bit of the OMAP4 data) and timer code. It is the first
prerequisite series to removing a big chunk of
Hi
On Tue, 31 Jan 2012, Cousson, Benoit wrote:
Thanks to the L3 log error:
[0.838439] L3 custom error: MASTER:DucatiM3 TARGET:GPMC
I guess that I understand why I was not releasing the hardreset at boot time
before:-)
DSP and CortexM3 cannot be released from reset until someone
On Mon, Jan 30, 2012 at 07:20:17PM -0600, Omar Ramirez Luna wrote:
There are two members of pr_ctxt allocated during bridge_open that
are never freed resulting in memory leaks, these are stream_id and
node_id, they are now freed on release of the handle (bridge_release)
right before freeing
On 1/31/2012 9:14 AM, Paul Walmsley wrote:
Hi
On Tue, 31 Jan 2012, Cousson, Benoit wrote:
Thanks to the L3 log error:
[0.838439] L3 custom error: MASTER:DucatiM3 TARGET:GPMC
I guess that I understand why I was not releasing the hardreset at boot time
before:-)
DSP and CortexM3 cannot be
On Mon, Jan 30, 2012 at 07:20:18PM -0600, Omar Ramirez Luna wrote:
This structure is still used after it has been freed, since it
is being allocated in probe, calls to free it have been moved to
module's remove routine.
This should fix the follwoing messages when attempting to remove the
On Tue, Jan 31, 2012 at 1:19 PM, Paul Walmsley p...@pwsan.com wrote:
On Tue, 31 Jan 2012, Shilimkar, Santosh wrote:
A week back I was discussing with Benoit and Tony about having some
infrastructure like unused clocks so that we can shutdown those
modules, and if possible some power domains.
On 31 January 2012 07:38, Shilimkar, Santosh santosh.shilim...@ti.com wrote:
On Tue, Jan 31, 2012 at 1:01 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On 31 January 2012 05:21, Aneesh V ane...@ti.com wrote:
On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote:
On Fri, Jan 20, 2012
On Tue, Jan 31, 2012 at 2:24 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On 31 January 2012 07:38, Shilimkar, Santosh santosh.shilim...@ti.com wrote:
On Tue, Jan 31, 2012 at 1:01 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On 31 January 2012 05:21, Aneesh V ane...@ti.com wrote:
Hi Kevin, Paul,
On Fri, Jan 27, 2012 at 3:03 PM, Sakari Ailus sakari.ai...@iki.fi wrote:
Hi Jean,
Thanks for you quick reply.
On Fri, Jan 27, 2012 at 12:06:37PM +0100, Jean Pihet wrote:
Hi,
On Fri, Jan 27, 2012 at 11:00 AM, Sakari Ailus sakari.ai...@iki.fi wrote:
MPU and CORE should
On 31 January 2012 09:05, Shilimkar, Santosh santosh.shilim...@ti.com wrote:
On Tue, Jan 31, 2012 at 2:24 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On 31 January 2012 07:38, Shilimkar, Santosh santosh.shilim...@ti.com
wrote:
On Tue, Jan 31, 2012 at 1:01 PM, Catalin Marinas
On Tue, Jan 31, 2012 at 02:35:51PM +0530, Shilimkar, Santosh wrote:
On Tue, Jan 31, 2012 at 2:24 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
Not if you write the code sequence in such a way that it also switches
the C bit to 0 and back to 1. I think Nicolas suggested that the
Integrate the latest SmartReflex bufixes from Felipe Balbi [1] and
Nishant Menon [2], plus misc bugfixes.
Based on latest master branch of the mainline git tree (3.3.0-rc1) [3], commit
27ba234c8dfe86c96675d4ef275d1d3c1f5f7053.
[1] http://marc.info/?l=linux-omapm=132134699423547w=2
[2]
From: Shweta Gulati shweta.gul...@ti.com
To set sr ntarget values for all volt_domain,
volt_table is retrieved by doing a look_up of 'vdd_name'
field from omap_hwmod but voltage domain pointer does not
belong to omap_hwmod and is not used anywhere else.
As a part of voltage layer and SR Layer
From: Julia Lawall ju...@diku.dk
At this point, the ioremap has taken place, so the error handling code at
the label err_iounmap should be used rather than returning directly.
The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
// smpl
@r@
identifier x;
@@
From: Nishanth Menon n...@ti.com
sr_modify_mask takes mask, value as parameters, the usage
currently is value, mask which is wrong, as a result
vpboundint_st which was supposed to have been disabled,
does not get disabled.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Jean Pihet
From: Nishanth Menon n...@ti.com
SmartReflex AVS Errorgen module supplies signals to Voltage
Processor. It is suggested that by disabling Errorgen module
before we disable VP, we might be able to ensure lesser
chances of race condition to occur in the system.
Signed-off-by: Nishanth Menon
From: Nishanth Menon n...@ti.com
Since OMAP's VP and PRM modules do not get reset by warm reset,
we should ensure that proper shutdown procedure is followed prior
to allowing the kernel to reboot back up.
Without this patch, Smartreflex module might be left active or
system might be caught in an
From: Nishanth Menon n...@ti.com
ERRCONFIG register has status bits that were intended not to
be destroyed by bad modification. We cleanup and simplify the
handling the status in the modify path.
Reported-by: Vincent Bour v-b...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by:
From: Nishanth Menon n...@ti.com
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
ERRCONFIG register's VPBOUNDINTST has an additional functional meaning
It force clears Sr_interruptz internal signal. This can result in
scenarios where VP- SR protocol is
From: Nishanth Menon n...@ti.com
OMAP3 SmartReflex IRQs in hwmod structures with the same naming as
present in OMAP4. Without these IRQs being registered, SmartReflex
driver will be unable to get the IRQ numbers to handle notifications
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by:
From: Nishanth Menon n...@ti.com
Certain class drivers such as class 1.5 drivers, will need specific
notification that they have to be inited up or deinited independent
of smart reflex operation. They also may need private data to be
used for operations of their own, provide the same.
This allows
From: Nishanth Menon n...@ti.com
SmartReflex IP V1 and V2 have different registers and offsets.
Currently, we pass the status as is to the class driver. However,
since we don't pass the version of the underlying SR hardware
to the Class driver, it will not be unable to make consistent
sense of
From: Nishanth Menon n...@ti.com
Introduce private data for class drivers to operate on per
voltage domain. This removes the necessity for drivers such
as SmartReflex AVS Class 1.5 drivers from maintaining
a special lookup table which does not scale when number of
voltage domains change depending
From: Felipe Balbi ba...@ti.com
That's very useful to fetch the correct struct sr_info
from the PM handlers.
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/smartreflex.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff
From: Nishanth Menon n...@ti.com
Use SmartReflex AVS Class3 initialization only for OMAP343x family of
processors.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/smartreflex-class3.c |5 +
1 files changed, 5 insertions(+), 0
From: Felipe Balbi ba...@ti.com
There are no functional changes here, only misc cleanups in general:
- re-organize variable declarations,
- converting if {} else if {} else {} into switch statements,
- correct comments typos,
- add/remove white lines to improve readability,
- etc.
Signed-off-by:
From: Felipe Balbi ba...@ti.com
no functional changes, trivial patch.
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/smartreflex.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
The debugfs_create_* API returns a NULL ptr in case of problem.
Fix the smartreflex code to take this into account.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git
From: Felipe Balbi ba...@ti.com
val (val != 1) == val 1
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/smartreflex.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
From: Nishanth Menon n...@ti.com
We need some mechanism from class drivers to control when notifiers
should be triggered and when not, currently we have none, which makes
Class driver usage of the interrupt events almost impossible.
We also ensure that disable/enable or irq is always guarenteed
From: Nishanth Menon n...@ti.com
At times with bad SR configurations, especially during silicon bring-ups,
we could get continuous spurious interrupts which end up hanging the
platform in the form of an ISR call for status bits that are
automatically enabled by the hardware without any software
On Tue, Jan 31, 2012 at 09:53:25AM +, Catalin Marinas wrote:
Maybe we could factor out the CPU-specific settings from proc-v*.S
into a separate arch/arm/boot/preload directory. We keep proc-v*.S
entirely generic and the implementation-defined bits setting in the
preload code. You could
Sergei,
On Thu, Jan 26, 2012 at 12:26 PM, Sergei Shtylyov
sshtyl...@ru.mvista.com wrote:
Hello.
On 25-01-2012 19:16, Jean Pihet wrote:
...
Change-Id: Id0145adacfa63d7652a29859ad6c95cc2ac61cc8
Please remove this line.
Done!
...
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
On Tue, Jan 31, 2012 at 3:26 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Jan 31, 2012 at 02:35:51PM +0530, Shilimkar, Santosh wrote:
On Tue, Jan 31, 2012 at 2:24 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
Not if you write the code sequence in such a way that it
Dear mailing-list,
I am working with a vanilla 3.0.17 kernel with some patch for my Omap4430 based
board.
I am using the driver video/omap2/panel-lgphilips-lb025q02.c with a very
similar screen.
I have added on my board init file the init code for both the SPI and the
panel, like below.
The debugfs_create_* API returns a NULL ptr in case of problem.
Fix the PM debug code to take this into account.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/pm-debug.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c
On Tue, Jan 31, 2012 at 11:05:43AM +0300, Dan Carpenter wrote:
On Tue, Jan 31, 2012 at 12:12:20AM +0100, Víctor Manuel Jáquez Leal wrote:
Silence the warning when compiling drv_interface.c
Signed-off-by: Víctor Manuel Jáquez Leal vjaq...@igalia.com
What does the compiler warn about
Hi,
On Tuesday 31 January 2012 04:26 PM, Patrick wrote:
Dear mailing-list,
I am working with a vanilla 3.0.17 kernel with some patch for my Omap4430 based
board.
I am using the driver video/omap2/panel-lgphilips-lb025q02.c with a very
similar screen.
I have added on my board init file the
On Tue, Jan 31, 2012 at 12:19:52PM +0100, Víctor M. Jáquez L. wrote:
On Tue, Jan 31, 2012 at 11:05:43AM +0300, Dan Carpenter wrote:
On Tue, Jan 31, 2012 at 12:12:20AM +0100, Víctor Manuel Jáquez Leal wrote:
Silence the warning when compiling drv_interface.c
Signed-off-by: Víctor
Hello.
On 31-01-2012 14:06, Jean Pihet wrote:
...
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+ u32 errconfig_offs, vpboundint_en;
+ u32 vpboundint_st;
+ struct omap_sr *sr = _sr_lookup(voltdm);
+
+ if (IS_ERR(sr)) {
+ pr_warning(%s: omap_sr
On Tue, Jan 31, 2012 at 3:48 AM, Paul Walmsley p...@pwsan.com wrote:
If the DEBOUNCENABLE bit is set and the debounce clock is off and the GPIO
IP block is idle, then yeah, I'd assume that GPIO wakeups would not
work.
But it sounds like they are working for you when DEBOUNCENABLE is set and
Hi,
On Tuesday 31 January 2012 04:26 PM, Patrick wrote:
Dear mailing-list,
I am working with a vanilla 3.0.17 kernel with some patch for my Omap4430
based board.
I am using the driver video/omap2/panel-lgphilips-lb025q02.c with a very
similar screen.
I have added on my board init file
On 31 January 2012 10:10, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Jan 31, 2012 at 09:53:25AM +, Catalin Marinas wrote:
Maybe we could factor out the CPU-specific settings from proc-v*.S
into a separate arch/arm/boot/preload directory. We keep proc-v*.S
entirely
Sergei,
On Tue, Jan 31, 2012 at 12:37 PM, Sergei Shtylyov
sshtyl...@ru.mvista.com wrote:
Hello.
On 31-01-2012 14:06, Jean Pihet wrote:
...
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+ u32 errconfig_offs, vpboundint_en;
+ u32 vpboundint_st;
+ struct
On 01/25/2012 03:04 PM, Daniel Lezcano wrote:
On 01/20/2012 09:40 PM, Colin Cross wrote:
On Fri, Jan 20, 2012 at 12:46 AM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
Hi Colin,
this patchset could be interesting to resolve in a generic way the cpu
dependencies.
What is the status of this
Hi Tony,
I am working on implementing pincontrol driver for AM335X SoC (OMAP34XX family).
Is there any specific plan you have in mind w.r.t incorporating
pincontrol driver for OMAP family of SoC's. There was an initial patch
for OMAP4 pin control driver, but it seems you were in favour of a
DT
Hi,
* Mohammed, Afzal af...@ti.com [120131 06:04]:
Hi Tony,
I am working on implementing pincontrol driver for AM335X SoC (OMAP34XX
family).
Is there any specific plan you have in mind w.r.t incorporating
pincontrol driver for OMAP family of SoC's. There was an initial patch
for OMAP4
* Jean Pihet jean.pi...@newoldbits.com [120131 01:28]:
Integrate the latest SmartReflex bufixes from Felipe Balbi [1] and
Nishant Menon [2], plus misc bugfixes.
We should move this to live under drivers somewhere. So
I'd like to see just minimal cleanup in the current location,
then move it to
Hi Tony,
On Tue, Jan 31, 2012 at 6:08 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [120131 01:28]:
Integrate the latest SmartReflex bufixes from Felipe Balbi [1] and
Nishant Menon [2], plus misc bugfixes.
We should move this to live under drivers
* Pihet-XID, Jean j-pi...@ti.com [120131 08:44]:
Hi Tony,
On Tue, Jan 31, 2012 at 6:08 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [120131 01:28]:
Integrate the latest SmartReflex bufixes from Felipe Balbi [1] and
Nishant Menon [2], plus misc
Jean Pihet jean.pi...@newoldbits.com writes:
Hi Kevin, Paul,
On Fri, Jan 27, 2012 at 3:03 PM, Sakari Ailus sakari.ai...@iki.fi wrote:
Hi Jean,
Thanks for you quick reply.
On Fri, Jan 27, 2012 at 12:06:37PM +0100, Jean Pihet wrote:
Hi,
On Fri, Jan 27, 2012 at 11:00 AM, Sakari Ailus
On Tue, Jan 31, 2012 at 6:20 PM, Tony Lindgren t...@atomide.com wrote:
* Pihet-XID, Jean j-pi...@ti.com [120131 08:44]:
Hi Tony,
On Tue, Jan 31, 2012 at 6:08 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [120131 01:28]:
Integrate the latest SmartReflex
Paul,
Kevin Hilman khil...@ti.com writes:
Paul Walmsley p...@pwsan.com writes:
Remove some superfluous calls to pwrdm_clear_all_prev_pwrst().
pwrdm_pre_transition(), which appears a few lines after these calls,
invokes pwrdm_clear_all_prev_pwrst() on each powerdomain -- there's no
need to
* Jean Pihet jean.pi...@newoldbits.com [120131 08:53]:
On Tue, Jan 31, 2012 at 6:20 PM, Tony Lindgren t...@atomide.com wrote:
* Pihet-XID, Jean j-pi...@ti.com [120131 08:44]:
Hi Tony,
On Tue, Jan 31, 2012 at 6:08 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet
Jean Pihet jean.pi...@newoldbits.com writes:
The debugfs_create_* API returns a NULL ptr in case of problem.
Fix the PM debug code to take this into account.
Signed-off-by: Jean Pihet j-pi...@ti.com
---
arch/arm/mach-omap2/pm-debug.c |4 ++--
1 files changed, 2 insertions(+), 2
On Tue, 31 Jan 2012, Catalin Marinas wrote:
Maybe we could factor out the CPU-specific settings from proc-v*.S
into a separate arch/arm/boot/preload directory. We keep proc-v*.S
entirely generic and the implementation-defined bits setting in the
preload code. You could have an option to link
On Tue, Jan 31, 2012 at 2:17 AM, Dan Carpenter dan.carpen...@oracle.com wrote:
On Mon, Jan 30, 2012 at 07:20:17PM -0600, Omar Ramirez Luna wrote:
There are two members of pr_ctxt allocated during bridge_open that
are never freed resulting in memory leaks, these are stream_id and
node_id, they
On Tue, Jan 31, 2012 at 2:21 AM, Dan Carpenter dan.carpen...@oracle.com wrote:
On Mon, Jan 30, 2012 at 07:20:18PM -0600, Omar Ramirez Luna wrote:
This structure is still used after it has been freed, since it
is being allocated in probe, calls to free it have been moved to
module's remove
On Tue, 31 Jan 2012, Shilimkar, Santosh wrote:
On Tue, Jan 31, 2012 at 3:26 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
So, as many people have said, we're not going to go down the route of
allowing platforms to hook into this code. There's plenty of other
solutions to
On Tue, Jan 31, 2012 at 12:09:17PM -0600, Omar Ramirez Luna wrote:
On Tue, Jan 31, 2012 at 2:17 AM, Dan Carpenter dan.carpen...@oracle.com
wrote:
On Mon, Jan 30, 2012 at 07:20:17PM -0600, Omar Ramirez Luna wrote:
There are two members of pr_ctxt allocated during bridge_open that
are never
On Tue, Jan 31, 2012 at 12:19:00PM -0600, Ramirez Luna, Omar wrote:
On Tue, Jan 31, 2012 at 2:21 AM, Dan Carpenter dan.carpen...@oracle.com
wrote:
On Mon, Jan 30, 2012 at 07:20:18PM -0600, Omar Ramirez Luna wrote:
This structure is still used after it has been freed, since it
is being
On Tue, Jan 31, 2012 at 8:43 PM, Dan Carpenter dan.carpen...@oracle.com wrote:
How often do people rmmod things on a production system? Hopefully,
never right?
That's right... At least in recent versions of the tidspbrdige, that
have recovery support. Before, we needed a script to detect MMU
Hi Grant,
On 1/28/2012 7:06 PM, Grant Likely wrote:
On Fri, Jan 27, 2012 at 06:29:22PM +0100, Cousson, Benoit wrote:
Add some basic helpers to retrieve a DMA controller device_node
and the DMA request line number.
For legacy reason another API will export the DMA request number
into a Linux
On Tue, Jan 31, 2012 at 1:39 PM, Grazvydas Ignotas nota...@gmail.com wrote:
So when does all wakeup stuff come into effect, when CORE+PER go to
low power state? I'm using 3.2 and CORE seems to always be ON
(regardless of cpuidle option) except when I suspend I guess. I can
get PER state to
Tony Lindgren t...@atomide.com writes:
* Jean Pihet jean.pi...@newoldbits.com [120131 08:53]:
On Tue, Jan 31, 2012 at 6:20 PM, Tony Lindgren t...@atomide.com wrote:
* Pihet-XID, Jean j-pi...@ti.com [120131 08:44]:
Hi Tony,
On Tue, Jan 31, 2012 at 6:08 PM, Tony Lindgren t...@atomide.com
On Sat, Jan 28, 2012 at 11:06:02AM -0700, Grant Likely wrote:
This makes the assumption that dma specifiers will only ever be 1
cell. I think to be generally useful, the full dma specifier needs to
be either handed to the dma controller to get a cookie or passed back
to the caller in its
* Kevin Hilman khil...@ti.com [120131 13:28]:
Tony Lindgren t...@atomide.com writes:
* Jean Pihet jean.pi...@newoldbits.com [120131 08:53]:
On Tue, Jan 31, 2012 at 6:20 PM, Tony Lindgren t...@atomide.com wrote:
* Pihet-XID, Jean j-pi...@ti.com [120131 08:44]:
Hi Tony,
On Tue,
From: Felipe Contreras felipe.contre...@nokia.com
The public images have it enabled, it's safer, and we get rid of this
warning:
WARNING: at arch/arm/mach-omap2/omap_l3_smx.c:162 omap3_l3_app_irq+0x114/0x15c()
In-band Error seen by IVA_SS at address 0
Modules linked in: bridgedriver(C+)
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
---
drivers/mfd/twl4030-irq.c | 26 ++
1 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index b69bb51..b31f920 100644
---
We enable power, but don't disable it in case of an error.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
---
drivers/power/isp1704_charger.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/power/isp1704_charger.c b/drivers/power/isp1704_charger.c
On Wed, Feb 01, 2012 at 03:01:32AM +0200, Felipe Contreras wrote:
From: Felipe Contreras felipe.contre...@nokia.com
The public images have it enabled, it's safer, and we get rid of this
warning:
WARNING: at arch/arm/mach-omap2/omap_l3_smx.c:162
omap3_l3_app_irq+0x114/0x15c()
In-band
On Wed, Feb 1, 2012 at 3:12 AM, Greg KH gre...@suse.de wrote:
On Wed, Feb 01, 2012 at 03:01:32AM +0200, Felipe Contreras wrote:
From: Felipe Contreras felipe.contre...@nokia.com
The public images have it enabled, it's safer, and we get rid of this
warning:
WARNING: at
Hi, Don
Thanks for your feedback!
Unfortunately, the hardlockup depends on NMI which is not available on
ARM (Cortex-A9) per my understanding.
Our system uses OMAP4430. Any more suggestions?
On Tue, Jan 31, 2012 at 11:47 PM, Don Zickus dzic...@redhat.com wrote:
On Tue, Jan 31, 2012 at
On Wed, Feb 01, 2012 at 03:37:55AM +0200, Felipe Contreras wrote:
On Wed, Feb 1, 2012 at 3:12 AM, Greg KH gre...@suse.de wrote:
On Wed, Feb 01, 2012 at 03:01:32AM +0200, Felipe Contreras wrote:
From: Felipe Contreras felipe.contre...@nokia.com
The public images have it enabled, it's
On Tue, 31 Jan 2012, Grazvydas Ignotas wrote:
On Tue, Jan 31, 2012 at 3:48 AM, Paul Walmsley p...@pwsan.com wrote:
If the DEBOUNCENABLE bit is set and the debounce clock is off and the GPIO
IP block is idle, then yeah, I'd assume that GPIO wakeups would not
work.
But it sounds like
On Tue, 31 Jan 2012, Grazvydas Ignotas wrote:
On Tue, Jan 31, 2012 at 1:39 PM, Grazvydas Ignotas nota...@gmail.com wrote:
So when does all wakeup stuff come into effect, when CORE+PER go to
low power state? I'm using 3.2 and CORE seems to always be ON
(regardless of cpuidle option) except
On Tue, 31 Jan 2012, Paul Walmsley wrote:
Well, whether it's in or out of idle, I'll bet the DEBOUNCENABLE
bits are still set to 1 while the debounce clock is off :-(
Along these lines, you might try patching omap2_gpio_prepare_for_idle() to
turn off the DEBOUNCENABLE bits?
- Paul
--
To
On Tue, 31 Jan 2012 22:47:32 -0700 (MST) Paul Walmsley p...@pwsan.com wrote:
Let me also answer the question from the MPU's perspective. Suppose the
MPU powerdomain has entered a low power state. That means that the MPU
INTC -- part of the MPU powerdomain -- is also in a low power state.
Add support for TWL4030, which is interfaced on i2c1 bus.
Also add clock frequencies for other i2c instances(2 3)
required for client-device exist on OMAP3EVM board.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Grant Likely grant.lik...@secretlab.ca
Cc:
TI's OMAP3EVM and AM335xEVM are software development boards
available for OMAP35x(AM/DM37x) and AM335x devices respectively;
and these devices are considered under omap3 family.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Grant Likely
On Tue, Jan 24, 2012 at 04:05:32, Hilman, Kevin wrote:
Hiremath, Vaibhav hvaib...@ti.com writes:
On Wed, Jan 11, 2012 at 21:48:25, Hiremath, Vaibhav wrote:
On Tue, Jan 10, 2012 at 23:39:22, Hilman, Kevin wrote:
Vaibhav Hiremath hvaib...@ti.com writes:
AM33XX PRM module (L4_WK
On Thu, Dec 08, 2011 at 22:48:54, Tony Lindgren wrote:
Russell,
* Hiremath, Vaibhav hvaib...@ti.com [111208 05:14]:
From: Tony Lindgren [mailto:t...@atomide.com]
* Kevin Hilman khil...@ti.com [111206 15:52]:
I've also tested it on a BeagleBone, so feel free to also add:
On Tue, Jan 31, 2012 at 09:39:00PM +0200, Felipe Contreras wrote:
On Tue, Jan 31, 2012 at 8:43 PM, Dan Carpenter dan.carpen...@oracle.com
wrote:
How often do people rmmod things on a production system? Hopefully,
never right?
That's right... At least in recent versions of the
On Wed, 1 Feb 2012, NeilBrown wrote:
On Tue, 31 Jan 2012 22:47:32 -0700 (MST) Paul Walmsley p...@pwsan.com wrote:
Let me also answer the question from the MPU's perspective. Suppose the
MPU powerdomain has entered a low power state. That means that the MPU
INTC -- part of the MPU
On Tue, Jan 31, 2012 at 11:57 PM, Nicolas Pitre n...@fluxnic.net wrote:
On Tue, 31 Jan 2012, Shilimkar, Santosh wrote:
[...]
I also understand that patching early common code is going to be tricky
and of-course against the single zImage.
So the option mentioned by Nicolas and Catalin about
Hi Arnd,
On Thu, Dec 22, 2011 at 5:22 PM, Arnd Bergmann a...@arndb.de wrote:
If you think you need more Acks or if there are other
reasons to have it go through arm-soc, please tell me and I'll try harder
to find the time for a proper review.
Any chance you could carve out some time for
On Wed, Feb 1, 2012 at 5:44 AM, Greg KH g...@kroah.com wrote:
On Wed, Feb 01, 2012 at 03:37:55AM +0200, Felipe Contreras wrote:
On Wed, Feb 1, 2012 at 3:12 AM, Greg KH gre...@suse.de wrote:
On Wed, Feb 01, 2012 at 03:01:32AM +0200, Felipe Contreras wrote:
From: Felipe Contreras
On Wed, Feb 1, 2012 at 8:58 AM, Dan Carpenter dan.carpen...@oracle.com wrote:
On Tue, Jan 31, 2012 at 09:39:00PM +0200, Felipe Contreras wrote:
On Tue, Jan 31, 2012 at 8:43 PM, Dan Carpenter dan.carpen...@oracle.com
wrote:
How often do people rmmod things on a production system? Hopefully,
Hi Paul,
On 01/25/2012 11:23 PM, Paul Walmsley wrote:
Okay, thanks, queued for 3.3-rc.
It seams this patch did not made it to 3.3-rc2.
We still have broken audio out of box on SDP4430/Blaze.
Can you make sure that this will be queued for rc3?
Thank you,
Péter
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On Fri, 27 Jan 2012 23:02:51 -0700 (MST) Paul Walmsley p...@pwsan.com wrote:
Since the HDQ module doesn't support the idle protocol, the target clock
FSM in the CM is what should determine whether the module is considered
idle or not. And as long as the bit in the CM_FCLKEN register
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