This will probably never fail but it's better style.
Signed-off-by: Mark Brown
---
sound/soc/omap/omap3pandora.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/sound/soc/omap/omap3pandora.c b/sound/soc/omap/omap3pandora.c
index 805512f..953483e 100644
--- a/sound/soc
On Saturday 02 March 2013 05:55 AM, Nishanth Menon wrote:
> On 17:41-20130301, Santosh Shilimkar wrote:
>> The OMAP5 idle driver can re-use OMAP4 CPUidle driver implementation thanks
>> to compatible MPUSS design.
>>
>> Though unlike OMAP4, on OMAP5 devices, MPUSS C
On Saturday 02 March 2013 05:26 AM, Nishanth Menon wrote:
> On 17:41-20130301, Santosh Shilimkar wrote:
>> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
>> b/arch/arm/mach-omap2/cpuidle44xx.c
>> index 9de47a7..df81243 100644
>> --- a/arch/arm/mach-omap2/cpuidle44xx.c
&
On Saturday 02 March 2013 05:13 AM, Nishanth Menon wrote:
> On 17:41-20130301, Santosh Shilimkar wrote:
>> When the entire MPUSS cluster is powered down in device off state, L2 cache
>> memory looses it's content and hence while targetting such a state,
>> l2 cache n
On Saturday 02 March 2013 03:23 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> While waking up CPU from off state using clock domain force wakeup, restore
>> the CPU power state to ON state before putting CPU clock domain under
>> hardware control.
On Saturday 02 March 2013 03:06 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> Add power management code to handle the CPU off mode. Separate
>> suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
>> use SCU power status regi
On Saturday 02 March 2013 01:42 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> With consolidated code, now we can add the .init_late hook for
>> OMAP5 to enable power management and mux initialization.
>>
>> Signed-off-by: Santosh Shilimka
On Saturday 02 March 2013 01:12 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> In addition to the standard power-management technique, the OMAP5
>> MPU subsystem also employs an SR3-APG (mercury) power management
>> technology to reduce leaka
On Saturday 02 March 2013 01:07 AM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> Enables MPUSS ES2 power management mode using ES2_PM_MODE in
>> AMBA_IF_MODE register.
>>
>> 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
On Friday 01 March 2013 11:13 PM, Nishanth Menon wrote:
> On 17:40-20130301, Santosh Shilimkar wrote:
>> diff --git a/arch/arm/mach-omap2/pm44xx.c
>> b/arch/arm/mach-omap2/pm_omap4plus.c
>> similarity index 74%
>> rename from arch/arm/mach-omap2/pm44xx.c
>&
On Friday 01 March 2013 10:52 PM, Jon Hunter wrote:
> For OMAP devices, if a gpio is being used as an interrupt source but has
> not been requested by calling gpio_request(), a call to request_irq()
> may cause the kernel hang because the gpio bank may be disabled and
> hence the register access wi
On Friday 01 March 2013 10:52 PM, Jon Hunter wrote:
> Currently the OMAP GPIO driver uses a legacy mapping for the GPIO IRQ
> domain. This is not necessary because we do not need to assign a
> specific interrupt number to the GPIO IRQ domain. Therefore, convert
> the OMAP GPIO driver to use a linea
On Fri, Feb 15, 2013 at 11:03 AM, Cousson, Benoit wrote:
> Hi Matthias,
>
>
> On 2/15/2013 10:35 AM, Matthias Brugger wrote:
>>
>> 2013/1/26 Javier Martinez Canillas :
>>>
>>> On Sat, Jan 26, 2013 at 4:16 PM, Matthias Brugger
>>>
>>> wrote:
Hi Benoit,
2012/12/12 Benoit Cousson
On 01.03.2013 22:57, Daniel Mack wrote:
> Hi Afzal, everyone,
>
> On 03.11.2012 08:33, Mohammed, Afzal wrote:
>> * Daniel Mack, November 03, 2012 1:06 AM:
>>
>>> I'm testing these patches with an AM33xx board that has the first musb
>>> port wired to an USB type A plug, but it doesn't yet work for
On 17:41-20130301, Santosh Shilimkar wrote:
> The OMAP5 idle driver can re-use OMAP4 CPUidle driver implementation thanks
> to compatible MPUSS design.
>
> Though unlike OMAP4, on OMAP5 devices, MPUSS CSWR (Close Switch Retention)
> power states can be achieved with respective
On 17:41-20130301, Santosh Shilimkar wrote:
> Current OMAP4 CPUIdle driver is using omap4_mpuss_read_prev_context_state()
> function to check whether the MPU cluster lost context or not. Thanks to
> couple CPUIdle, cluster low power entry is almost guaranteed and hence
> the progra
On Fri, Mar 01, 2013 at 04:41:37PM -0600, Jon Hunter wrote:
> Thanks for the history. For OMAP I see SMC_IRQ_FLAGS getting defined as
> follows in smc91x.h ...
>
> #ifndef SMC_IRQ_FLAGS
> #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
> #endif
>
> And so for OMAP devices using smc91x, it is
On 17:41-20130301, Santosh Shilimkar wrote:
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c
> b/arch/arm/mach-omap2/cpuidle44xx.c
> index 9de47a7..df81243 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
[...]
> @@ -234,11 +23
On Fri, Mar 01, 2013 at 12:09:12PM +0200, Ивайло Димитров wrote:
> Unfortunately it is necessary, on RX-51 PPA/NOLO leaves IBE bit unset.
You sure? I think you need to explain this more - the commit message in
the original patch is empty/missing...
A.
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To unsubscribe from this list: send the li
On 17:41-20130301, Santosh Shilimkar wrote:
> When the entire MPUSS cluster is powered down in device off state, L2 cache
> memory looses it's content and hence while targetting such a state,
> l2 cache needs to be flushed to main memory.
>
> Add the necessary low power code
On Fri, Mar 1, 2013 at 6:22 PM, Jon Hunter wrote:
> Summary of updates:
> - Convert OMAP GPIO driver to use linear mapping for IRQ domains
> - Avoid crashes seen if a gpio bank is not enabled when requesting an IRQ.
>
> Testing includes:
> - Boot testing on OMAP5912 OSK, OMAP2420 H4, OMAP3430 SDP,
On 03/01/2013 11:30 AM, Russell King - ARM Linux wrote:
> On Fri, Mar 01, 2013 at 05:17:57PM +0100, Javier Martinez Canillas wrote:
unsigned long irq_flags = SMC_IRQ_FLAGS;
...
if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK)
irq_flags = ires->flag
On 03/01/2013 02:12 PM, Ezequiel Garcia wrote:
> On Fri, Mar 1, 2013 at 5:11 PM, Ezequiel Garcia wrote:
>> Hi Jon,
>>
>> On Tue, Feb 26, 2013 at 2:30 PM, Jon Hunter wrote:
>> [...]
>>>
>>> + if (!of_property_read_u32(np, "gpmc,bus-turnaround", &val))
>>> + gpmc_t->bus_turnaro
On 03/01/2013 02:11 PM, Ezequiel Garcia wrote:
> Hi Jon,
>
> On Tue, Feb 26, 2013 at 2:30 PM, Jon Hunter wrote:
> [...]
>>
>> + if (!of_property_read_u32(np, "gpmc,bus-turnaround", &val))
>> + gpmc_t->bus_turnaround = val;
>> +
>
> AFAIK, you don't need to test if the prope
On 03/01/2013 03:25 PM, Ezequiel Garcia wrote:
> Hi Jon,
>
> On Tue, Feb 26, 2013 at 2:30 PM, Jon Hunter wrote:
> [...]
>> +static int gpmc_probe_nor_child(struct platform_device *pdev,
>> + struct device_node *child)
>> +{
>> + struct gpmc_settings gpmc_s;
>>
On 03/01/2013 03:42 PM, Ezequiel Garcia wrote:
> On Fri, Mar 1, 2013 at 6:08 PM, Ezequiel Garcia wrote:
>> Hi Jon,
>>
>> Yet more questions :-) See below...
>>
>> On Wed, Feb 13, 2013 at 7:07 PM, Jon Hunter wrote:
>>>
>>>
>>> You don't need this extra entry if you add "simple-bus" to
>>> the gpm
On 17:40-20130301, Santosh Shilimkar wrote:
> In MPUSS OSWR(Open Switch Retention), entire CPU cluster is powered down
> except L2 cache memory. For MPUSS OSWR state, both CPU's needs to be in
> power off state.
>
> Signed-off-by: Santosh Shilimkar
> ---
> arch
Hi Afzal, everyone,
On 03.11.2012 08:33, Mohammed, Afzal wrote:
> * Daniel Mack, November 03, 2012 1:06 AM:
>
>> I'm testing these patches with an AM33xx board that has the first musb
>> port wired to an USB type A plug, but it doesn't yet work for me.
>
>> So there is no host interface register
On 17:40-20130301, Santosh Shilimkar wrote:
> While waking up CPU from off state using clock domain force wakeup, restore
> the CPU power state to ON state before putting CPU clock domain under
> hardware control. Otherwise CPU wakeup might fail. The change is recommended\
the trail
On Fri, Mar 1, 2013 at 6:08 PM, Ezequiel Garcia wrote:
> Hi Jon,
>
> Yet more questions :-) See below...
>
> On Wed, Feb 13, 2013 at 7:07 PM, Jon Hunter wrote:
>>
>>
>> You don't need this extra entry if you add "simple-bus" to
>> the gpmc node compatible string.
>>
>> + gpmc: gpmc@
On 17:40-20130301, Santosh Shilimkar wrote:
> Add power management code to handle the CPU off mode. Separate
> suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
> use SCU power status register and external PL310 L2 cache which makes
> code flow bit different.
&
Hi Jon,
On Tue, Feb 26, 2013 at 2:30 PM, Jon Hunter wrote:
[...]
> +static int gpmc_probe_nor_child(struct platform_device *pdev,
> + struct device_node *child)
> +{
> + struct gpmc_settings gpmc_s;
> + struct gpmc_timings gpmc_t;
> + struct resourc
Hi Jon,
Yet more questions :-) See below...
On Wed, Feb 13, 2013 at 7:07 PM, Jon Hunter wrote:
>
>
> You don't need this extra entry if you add "simple-bus" to
> the gpmc node compatible string.
>
> + gpmc: gpmc@6800a000 {
> + compatible = "ti,omap2420-gpmc",
On Fri, Mar 1, 2013 at 2:25 PM, Matthias Brugger wrote:
> Hi Andreas,
>
> 2013/2/28 Andreas Müller :
>> Hi,
>>
>> I am preparing 3.8 mainline for gumstix overo and have the following
>> issue: waking Monitor connected by HDMI from power save makes Monitor
>> complain for unsupported frequency and
Ping. Any objections to that patch?
On Thu, Jan 24, 2013 at 7:34 PM, Marek Belisko
wrote:
> Signed-off-by: Marek Belisko
> ---
> arch/arm/boot/dts/omap3-gta04.dts | 94
> +
> 1 file changed, 94 insertions(+)
> create mode 100644 arch/arm/boot/dts/omap3-gt
On 17:40-20130301, Santosh Shilimkar wrote:
> With consolidated code, now we can add the .init_late hook for
> OMAP5 to enable power management and mux initialization.
>
> Signed-off-by: Santosh Shilimkar
> ---
> arch/arm/mach-omap2/board-generic.c |1 +
> arch/ar
On Fri, Mar 1, 2013 at 5:11 PM, Ezequiel Garcia wrote:
> Hi Jon,
>
> On Tue, Feb 26, 2013 at 2:30 PM, Jon Hunter wrote:
> [...]
>>
>> + if (!of_property_read_u32(np, "gpmc,bus-turnaround", &val))
>> + gpmc_t->bus_turnaround = val;
>> +
>
> AFAIK, you don't need to test if the
Hi Jon,
On Tue, Feb 26, 2013 at 2:30 PM, Jon Hunter wrote:
[...]
>
> + if (!of_property_read_u32(np, "gpmc,bus-turnaround", &val))
> + gpmc_t->bus_turnaround = val;
> +
AFAIK, you don't need to test if the property is defined.
You can just read it straightforward, and if the
On 17:40-20130301, Santosh Shilimkar wrote:
> In addition to the standard power-management technique, the OMAP5
> MPU subsystem also employs an SR3-APG (mercury) power management
> technology to reduce leakage.
Mercury fast is employed here - might be good to note that.
>
> It
On 17:40-20130301, Santosh Shilimkar wrote:
> Enables MPUSS ES2 power management mode using ES2_PM_MODE in
> AMBA_IF_MODE register.
>
> 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together. Broken
> 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mod
From: Randy Dunlap
Fix kernel-doc warnings in hsi files:
Warning(include/linux/hsi/hsi.h:136): Excess struct/union/enum/typedef member
'e_handler' description in 'hsi_client'
Warning(include/linux/hsi/hsi.h:136): Excess struct/union/enum/typedef member
'pclaimed' description in 'hsi_client'
Wa
On 17:40-20130301, Santosh Shilimkar wrote:
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm_omap4plus.c
> similarity index 74%
> rename from arch/arm/mach-omap2/pm44xx.c
> rename to arch/arm/mach-omap2/pm_omap4plus.c
> index 1d03110..95d2712 100644
> --- a/a
Jon Hunter writes:
> Summary of updates:
> - Convert OMAP GPIO driver to use linear mapping for IRQ domains
> - Avoid crashes seen if a gpio bank is not enabled when requesting an IRQ.
Acked-by: Kevin Hilman
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To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of
On 17:40-20130301, Santosh Shilimkar wrote:
> On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
> so that same code works for OMAP4+ devices.
>
> Signed-off-by: Santosh Shilimkar
Acked-by: Nishanth Menon
--
Regards,
Nishanth Menon
--
To unsubscribe from this li
On Fri, Mar 01, 2013 at 05:17:57PM +0100, Javier Martinez Canillas wrote:
> >> unsigned long irq_flags = SMC_IRQ_FLAGS;
> >> ...
> >>if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK)
> >> irq_flags = ires->flags & IRQF_TRIGGER_MASK;
> >>
> >> while smsc911x driver's pr
For OMAP devices, if a gpio is being used as an interrupt source but has
not been requested by calling gpio_request(), a call to request_irq()
may cause the kernel hang because the gpio bank may be disabled and
hence the register access will fail. To prevent such hangs, test for
this case and warn
Currently the OMAP GPIO driver uses a legacy mapping for the GPIO IRQ
domain. This is not necessary because we do not need to assign a
specific interrupt number to the GPIO IRQ domain. Therefore, convert
the OMAP GPIO driver to use a linear mapping instead.
Please note that this also allows to sim
Summary of updates:
- Convert OMAP GPIO driver to use linear mapping for IRQ domains
- Avoid crashes seen if a gpio bank is not enabled when requesting an IRQ.
Testing includes:
- Boot testing on OMAP5912 OSK, OMAP2420 H4, OMAP3430 SDP, OMAP4430 SDP
and AM335x EVM.
- Verified that GPIO interrupt
Hi Jon,
NOTE: I'm changing $subject to something more relevant to stop adding
noise on the original thread.
On Thu, Feb 28, 2013 at 9:49 PM, Jon Hunter wrote:
>
> On 02/28/2013 06:17 AM, Javier Martinez Canillas wrote:
>> On Thu, Feb 28, 2013 at 12:16 AM, Jon Hunter wrote:
>>>
>>> On 02/26/2013
On 02/28/2013 11:40 PM, Philip, Avinash wrote:
> On Thu, Feb 28, 2013 at 21:32:01, Hunter, Jon wrote:
>>
>> On 02/28/2013 04:38 AM, Philip, Avinash wrote:
>>> On Tue, Feb 26, 2013 at 23:00:33, Hunter, Jon wrote:
Convert the OMAP2+ NAND code to use the gpmc_cs_program_settings()
function
On 02/28/2013 11:33 PM, Philip, Avinash wrote:
> On Thu, Feb 28, 2013 at 22:42:37, Hunter, Jon wrote:
>>
>> On 02/28/2013 09:52 AM, Jon Hunter wrote:
>>>
>>> On 02/28/2013 12:05 AM, Philip, Avinash wrote:
On Tue, Feb 26, 2013 at 23:00:31, Hunter, Jon wrote:
> The GPMC has various differen
On Fri, Mar 1, 2013 at 1:47 AM, Ивайло Димитров wrote:
>
> They look similar, but they are not equivalent :). The first major difference
> is here (code taken from omap-smc.S)
>
>> ENTRY(omap_smc2)
>> stmfd sp!, {r4-r12, lr}
>> mov r3, r2
>> mov r2, r1
>>
Matthieu CASTET a écrit :
> Hi Paul,
>
> Paul Walmsley a écrit :
>> Hi Matthieu,
>>
>> On Tue, 22 Jan 2013, Paul Walmsley wrote:
>>
>>> Any progress on updating and resending your "omap3 nand : use
>>> NAND_BUSWIDTH_AUTO" patch? We're in danger of missing the 3.9 merge
>>> window if it takes to
On 17:40-20130301, Santosh Shilimkar wrote:
> arch/arm/mach-omap2/omap-mpuss-lowpower.c | 56
> +++--
> 1 file changed, 45 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
> b/arch/arm/mach-omap2/omap-mpuss-
Hi Andreas,
2013/2/28 Andreas Müller :
> Hi,
>
> I am preparing 3.8 mainline for gumstix overo and have the following
> issue: waking Monitor connected by HDMI from power save makes Monitor
> complain for unsupported frequency and console says:
>
> | omapdss APPLY error: FIFO UNDERFLOW on gfx, dis
On Friday 01 March 2013 06:43 PM, Nishanth Menon wrote:
> On 18:39-20130301, Santosh Shilimkar wrote:
>> On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
>>> $subject - warm reset
>>>
>> ok
>>> On 17:41-20130301, Santosh Shilimkar wrote:
>>&g
On 18:39-20130301, Santosh Shilimkar wrote:
> On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
> > $subject - warm reset
> >
> ok
> > On 17:41-20130301, Santosh Shilimkar wrote:
> >> From: Nishanth Menon
> >>
> >> OMAP5 and OMAP4 have
On Friday 01 March 2013 06:34 PM, Nishanth Menon wrote:
> $subject - warm reset
>
ok
> On 17:41-20130301, Santosh Shilimkar wrote:
>> From: Nishanth Menon
>>
>> OMAP5 and OMAP4 have different device instance offsets.
>>
>> So to handle them properly,
On 01/03/13 05:49, AnilKumar, Chimata wrote:
> On Wed, Feb 27, 2013 at 21:14:25, Mark Jackson wrote:
>> I've specified an I2C bus and all 6 UARTs in the dts file for my custom cpu
>> board, as follows:-
>>
>> ocp {
>> uart1: serial@44e09000 {
>> pinctrl-names
$subject - warm reset
On 17:41-20130301, Santosh Shilimkar wrote:
> From: Nishanth Menon
>
> OMAP5 and OMAP4 have different device instance offsets.
>
> So to handle them properly, use a runtime detected instance offset
> Other bit offsets and register offsets remained const
OMAP5 has backward compatible PRCM block and it's programming
model is mostly similar to OMAP4. Same is going to be maintained
for future OMAP4 based SOCs. Hence consolidate the OMAP4 power
management code so that it can be re-used on OMAP5 and later devices.
With consolidated code, let basic powe
From: Nishanth Menon
OMAP5 and OMAP4 have different device instance offsets.
So to handle them properly, use a runtime detected instance offset
Other bit offsets and register offsets remained constant.
Creating a new function is not really worthwhile here as the logic
will be replicated without
Current OMAP4 CPUIdle driver is using omap4_mpuss_read_prev_context_state()
function to check whether the MPU cluster lost context or not. Thanks to
couple CPUIdle, cluster low power entry is almost guaranteed and hence
the programmed cluster check is enough in idle exit path. The API was
more of a
When the entire MPUSS cluster is powered down in device off state, L2 cache
memory looses it's content and hence while targetting such a state,
l2 cache needs to be flushed to main memory.
Add the necessary low power code support for the same.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-
The OMAP5 idle driver can re-use OMAP4 CPUidle driver implementation thanks
to compatible MPUSS design.
Though unlike OMAP4, on OMAP5 devices, MPUSS CSWR (Close Switch Retention)
power states can be achieved with respective power states on CPU0 and CPU1
power domain. This mode was broken on OMAP4
Add power management code to handle the CPU off mode. Separate
suspend finisher is used for OMAP5(Cortex-A15) because it doesn't
use SCU power status register and external PL310 L2 cache which makes
code flow bit different.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-mpuss-lowp
With consolidated code, now we can add the .init_late hook for
OMAP5 to enable power management and mux initialization.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/board-generic.c |1 +
arch/arm/mach-omap2/common.h|3 ++-
arch/arm/mach-omap2/io.c|8 ++
The OMAP5 idle driver can re-use most of OMAP4 CPUidle driver
implementation. Also the next derivative SOCs are going to re-use
the MPUSS so, same driver with minor updates can be re-used.
Prepare the code so that its easier to add CPUidle support for
OMAP5 devices.
Signed-off-by: Santosh Shilimk
While waking up CPU from off state using clock domain force wakeup, restore
the CPU power state to ON state before putting CPU clock domain under
hardware control. Otherwise CPU wakeup might fail. The change is recommended\
for all OMAP4+ devices though the PRCM weakness was observed on OMAP5
devic
In MPUSS OSWR(Open Switch Retention), entire CPU cluster is powered down
except L2 cache memory. For MPUSS OSWR state, both CPU's needs to be in
power off state.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |2 ++
arch/arm/mach-omap2/omap-secure.h |
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: ES1 behavior, CPU cores would enter and exit OFF mode together. Broken
0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode independently.
This is one time settings thanks to always ON domain.
Sig
In addition to the standard power-management technique, the OMAP5
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU.
Signed-off-by: Santosh Shilimkar
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/om
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
c
OMAP5 and future OMAP based SOCs has backward compatible MPUSS
IP block with OMAP4. It's programming model is mostly similar.
Hence consolidate the OMAP MPUSS code so that it can be re-used
on OMAP5 and future SOCs.
No functional change.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/
Series adds OMAP5 MPUSS power management support for system wide suspend
and CPUidle. Its heavy re-use from OMAP4 and hence only ~390 odd lines are
needed to add OMAP5 PM support on top of existing OMAP4 PM support.
OMAP5 adds a mercury retention feature which is an enhancement of
existing retenti
Unfortunately it is necessary, on RX-51 PPA/NOLO leaves IBE bit unset.
> Оригинално писмо
>От: Peter De Schrijver
>Относно: Re: [PATCH] arm: omap: RX-51: ARM errata 430973 workaround
>До: Pali Rohár
>Изпратено на: Петък, 2013, Март 1 11:43:14 EET
>
>
>On Thu, Feb 28,
On Thu, Feb 28, 2013 at 10:42:28AM +0100, Pali Rohár wrote:
> Signed-off-by: Ivaylo Dimitrov
> Signed-off-by: Pali Rohár
> ---
> arch/arm/mach-omap2/Makefile|1 +
> arch/arm/mach-omap2/board-rx51-secure.c | 66
> +++
> arch/arm/mach-omap2/board-rx51
Hi all,
we've built a beagleboard xm clone last year and successfully managed to get it
running it at 1GHz with a 3.1 kernel. Our current 3.3 kernel only runs at
800MHz stabely. This fact and some issues we've been having with the USB stack
make us want to update to a more recent kernel version
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