Hi
just one comment.
On 10/03/13 02:07, Grazvydas Ignotas wrote:
On pandora, STS_USB interrupt doesn't arrive on USB host cable disconnect
for some reason while VBUS is driven by twl itself, but STS_HW_CONDITIONS
is updated correctly. It does work fine when PHY is powered down though.
To
On Sun, Mar 10, 2013 at 1:03 PM, Michael Trimarchi
mich...@amarulasolutions.com wrote:
Hi
just one comment.
On 10/03/13 02:07, Grazvydas Ignotas wrote:
On pandora, STS_USB interrupt doesn't arrive on USB host cable disconnect
for some reason while VBUS is driven by twl itself, but
Besides being used to interface with external memory devices,
the General-Purpose Memory Controller can be used to connect
Pseudo-SRAM devices such as ethernet controllers to OMAP2+
processors using the GPMC as a data bus.
The actual mapping between the GPMC address space and OMAP2+
address space
On Monday 04 March 2013 11:59 PM, Nishanth Menon wrote:
On 11:17-20130302, Santosh Shilimkar wrote:
On Saturday 02 March 2013 01:07 AM, Nishanth Menon wrote:
On 17:40-20130301, Santosh Shilimkar wrote:
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
[..]
Hi GraÅžvydas,
On Sun, 10 Mar 2013, Grazvydas Ignotas wrote:
For some unknown reason, allowing hwmod to control MIDLEMODE causes
core_pwrdm to not hit idle states for musb in DM3730 at least.
I've verified that setting any MIDLEMODE value other than force
standby before enabling the device
Hi Jon,
sorry for the delay,
On Tue, 5 Feb 2013, Jon Hunter wrote:
I noticed on my OMAP4430 SDP that in suspend L3INIT was failing to enter
retention state. I am not sure if this is the same problem that you are
seeing or not. However, I found that the reason the L3INIT was not entering
Hi Jon,
On Fri, Mar 8, 2013 at 10:57 PM, Jon Hunter jon-hun...@ti.com wrote:
Adds basic device-tree support for OMAP3430 SDP board which has 256MB
of RAM and uses the TWL4030 power management IC.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/boot/dts/Makefile |1 +
From: Nishanth Menon n...@ti.com
As per JESD209-2E specification for LPDDR2,
http://www.jedec.org/standards-documents/results/jesd209-2E
Table 73, LPDDR2 memories come in two flavors - Standard and
Extended. The Standard types can operate from -25C to +85C
However, beyond that and upto
From: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
The issue was that only the first timings table was added to the
emif platform data at the emif driver registration. All other
timings tables was filled with zeros. Now all emif timings table
are added to the platform data.
Signed-off-by:
of_get_property returns value in Big Endian format.
Before using this value it should be converted to little endian
using be32_to_cpup().
Custom configs of emif are read from dt using of_get_property,
but these are not converted to litte endian format.
Correcting the same here.
Signed-off-by:
From: Nishanth Menon n...@ti.com
In case the custom timings provide values which overflow
the maximum possible field value, warn and use maximum
permissible value.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/memory/emif.c | 36
From: Nishanth Menon n...@ti.com
Some machine or kernel variants might have missed implementation
of power off handlers. We DONOT want to let the system be in
out of spec state in this condition. So, WARN and attempt
a machine restart in the hopes of clearing the out-of-spec
temperature
This series resolves a few minor issues for EMIF driver.
Tested all patches on OMAP4430-sdp.
Patch : memory: emif: setup LP settings on freq update
is tested on a local tree, since freq update cannot be
tested on mainline.
Ambresh K (1):
memory: emif: setup LP settings on freq update
Grygorii
From: Ambresh K ambr...@ti.com
Program the power management shadow register on freq update
Else the concept of threshold frequencies dont really matter
as the system always uses the performance mode timing for LP
which is programmed in at init time.
Signed-off-by: Nishanth Menon n...@ti.com
From: Grygorii Strashko grygorii.stras...@ti.com
ERRATA DESCRIPTION :
The EMIF supports power-down state for low power. The EMIF
automatically puts the SDRAM into power-down after the memory is
not accessed for a defined number of cycles and the
EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is
The driver tries to round up the specified timeout cycles to
the next power of 2 value. But this is done wrongly.
Correcting this here.
Reported-by: Nishanth Menon n...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/memory/emif.c |4 ++--
1 file changed, 2 insertions(+), 2
minor nit.
$subject
s/Correct/Fix
On Monday 11 March 2013 10:35 AM, Lokesh Vutla wrote:
The driver tries to round up the specified timeout cycles to
the next power of 2 value. But this is done wrongly.
Correcting this here.
Change needs to be improved here. See below.
Reported-by: Nishanth
On Monday 11 March 2013 10:35 AM, Lokesh Vutla wrote:
From: Ambresh K ambr...@ti.com
Program the power management shadow register on freq update
Else the concept of threshold frequencies dont really matter
as the system always uses the performance mode timing for LP
which is programmed in
On Monday 11 March 2013 10:36 AM, Lokesh Vutla wrote:
From: Nishanth Menon n...@ti.com
In case the custom timings provide values which overflow
the maximum possible field value, warn and use maximum
permissible value.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Lokesh Vutla
Hi,
On Friday 08 March 2013 05:21 PM, Tomi Valkeinen wrote:
The DISPC channel used for each output is currently passed in panel
platform data from the board files.
To simplify this, and to make the panel drivers less dependent on OMAP,
this patch changes omapdss to resolve the channel
On Monday 11 March 2013 10:36 AM, Lokesh Vutla wrote:
From: Nishanth Menon n...@ti.com
As per JESD209-2E specification for LPDDR2,
http://www.jedec.org/standards-documents/results/jesd209-2E
Table 73, LPDDR2 memories come in two flavors - Standard and
Extended. The Standard types can
On Monday 11 March 2013 10:36 AM, Lokesh Vutla wrote:
From: Nishanth Menon n...@ti.com
Some machine or kernel variants might have missed implementation
of power off handlers. We DONOT want to let the system be in
out of spec state in this condition. So, WARN and attempt
a machine restart in
$subject is too vague. What issue ?
Some thing like Fix the incorrect 'size' parameter in memcpy' etc
On Monday 11 March 2013 10:36 AM, Lokesh Vutla wrote:
From: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
The issue was that only the first timings table was added to the
emif platform
On Monday 11 March 2013 10:36 AM, Lokesh Vutla wrote:
From: Grygorii Strashko grygorii.stras...@ti.com
ERRATA DESCRIPTION :
The EMIF supports power-down state for low power. The EMIF
automatically puts the SDRAM into power-down after the memory is
not accessed for a defined number of cycles
On Monday 11 March 2013 10:36 AM, Lokesh Vutla wrote:
of_get_property returns value in Big Endian format.
Before using this value it should be converted to little endian
using be32_to_cpup().
Custom configs of emif are read from dt using of_get_property,
but these are not converted to litte
On Friday 08 March 2013 05:21 PM, Tomi Valkeinen wrote:
The DISPC channel used for each output is currently passed in panel
platform data from the board files.
To simplify this, and to make the panel drivers less dependent on OMAP,
this patch changes omapdss to resolve the channel
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