Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch[1], which is just the
basic idea of adding dual/quad support in spi framework.
$subject patch will undergo changes
This patch series add support for ti qspi controller.
Adapted this series on top of Mark brown series[1]:
[1]: https://patchwork.kernel.org/patch/2834694/
Sourav Poddar (2):
drivers: spi: Add qspi flash controller
driver: spi: Add quad spi read support
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will
On Saturday 03 August 2013 03:58 AM, Santosh Shilimkar wrote:
On Tuesday 30 July 2013 07:25 AM, Rajendra Nayak wrote:
Changes in v2:
-1- Fixed minor changelog details
-2- Dropped the SRAM support patch since we need to move to
drivers/misc/sram.c
-3- Added DTS update patches to this series
From: R Sricharan r.sricha...@ti.com
The PRCM and MPUSS parts of DRA7 devices are quite identical
to OMAP5 so as to reuse all the existing infrastructure around it.
Makefile updates to do just that.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
From: R Sricharan r.sricha...@ti.com
All of OMAP5 timer support for clocksource and clockevent is completely
reused across DRA7.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
From: R Sricharan r.sricha...@ti.com
Describe minimal DT boot machine details for DRA7xx based SoC's. DRA7xx
family is based on dual core ARM CORTEX A15 using GIC as the interrupt
controller.
The PRCM and timer infrastructure is reused from OMAP5 and so are the io
descriptor tables.
From: R Sricharan r.sricha...@ti.com
The IO descriptor tables for DRA7 are a complete reuse from OMAP5.
A new dra7xx_init_early() does the base address inits.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Acked-by: Santosh Shilimkar
Changes in v3:
-1- Dropped some clock/dpll framework builds for dra7
-2- Added all instances of IPs in dtsi file
-3- dtsi does a 'disabled' by default and dts enables as needed
-4- soc_is_dra7xx() based on DT compatible instead of using ID code
Changes in v2:
-1- Fixed minor changelog details
-2-
From: R Sricharan r.sricha...@ti.com
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
and other TWL GPIOs, ARCH_NR_GPIO is set to 512 using the
kconfig default for DRA7.
Signed-off-by: R Sricharan r.sricha...@ti.com
From: R Sricharan r.sricha...@ti.com
Now that the needed pieces for DRA7 based SoCs' is present, enable
the build support in omap2plus_defconfig
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for
From: R Sricharan r.sricha...@ti.com
The DRA7xx is a high-performance, infotainment application device,
based on enhanced OMAP architecture integrated on a 28-nm technology.
Since DRA7 is a platform supported only using DT, the cpu detection
is based on the compatibles passed from DT blobs as
The soc_ops for dra7xx devices can be completed reused
from the ones used for omap4 and omap5 devices.
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |2 +-
1
On Tue, Jul 30, 2013 at 06:30:52AM -0700, Tony Lindgren wrote:
The following changes since commit ad81f0545ef01ea651886dddac4bef6cec930092:
Linux 3.11-rc1 (2013-07-14 15:18:27 -0700)
are available in the git repository at:
On Tue, Jul 30, 2013 at 06:33:36AM -0700, Tony Lindgren wrote:
Arnd Olof,
Can you please take this pull request directly? Other than the
omap5 regulator dts changes I just posted I don't yet have
anything else queued up right now.
Pulled. But Paul, if you don't mind, please base your
On Sun, 4 Aug 2013, Olof Johansson wrote:
On Tue, Jul 30, 2013 at 06:33:36AM -0700, Tony Lindgren wrote:
Arnd Olof,
Can you please take this pull request directly? Other than the
omap5 regulator dts changes I just posted I don't yet have
anything else queued up right now.
On Sun, Aug 4, 2013 at 4:46 PM, Paul Walmsley p...@pwsan.com wrote:
On Sun, 4 Aug 2013, Olof Johansson wrote:
On Tue, Jul 30, 2013 at 06:33:36AM -0700, Tony Lindgren wrote:
Arnd Olof,
Can you please take this pull request directly? Other than the
omap5 regulator dts changes I just
Hi Muguthan,
On Saturday 03 August 2013 05:19 PM, Mugunthan V N wrote:
On 8/2/2013 7:16 PM, Afzal Mohammed wrote:
+ mac: ethernet@4a10 {
+ compatible = ti,am4372-cpsw,ti,cpsw;
compatibility ti,am4372-cpsw is not needed as driver has only ti,cpsw
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