On 04/11/2014 02:47 AM, Tony Lindgren wrote: While debugging legacy
mode vs device tree booted PM regressions,
I noticed that omap3 is not toggling sys_clkreq and sys_off_mode
pins like it should.
The sys_clkreq and sys_off_mode pins are not toggling because of
the following issues:
1.
On 04/01/2014 08:13 PM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [140401 01:38]:
On 04/01/2014 01:09 AM, Tony Lindgren wrote:
We don't want to make access to these registers available without
proper frameworks as that will lead into misuse by various drivers.
And cleaning up that
On 03/04/2014 06:19 PM, Tero Kristo wrote:
Hi,
This set cleans up the CM/PRM codebase a bit, removing the need for direct
CM/PRM register access macros outside CM/PRM drivers. This is done in
preparation to isolate these drivers into its own driver directory.
Currently my plan is to create a
* Tero Kristo t-kri...@ti.com [140412 03:25]:
Just letting you know, that I created a kind of v2 for this set,
however I am not going to post it publicly before the pre-reqs for
this set are covered, basically the OMAP2 clock DT set. CM/PRM
cleanup set is outdated with this series though
* Tero Kristo t-kri...@ti.com [140412 02:01]:
On 04/11/2014 02:47 AM, Tony Lindgren wrote:
@@ -282,6 +283,7 @@ void omap_sram_idle(void)
/* CORE */
if (core_next_state PWRDM_POWER_ON) {
+ omap3_vc_set_pmic_signaling(core_next_state);
if (core_next_state
Add support for VAR-SOM-OM44[1] SODIMM system on module from Variscite. SoM
features a OMAP4460, 1GB RAM, Gigabit Ethernet (LAN7500) and optional WLAN/BT.
Also add support for VAR-STK-OM44 development board from Variscite. This kit
features a VAR-SOM-OM44 and the carrier board
Hi,
I getting the following error on Linus master right now.
[ 2.166320] WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:113
l3_interrupt_handler+0xf4/0x154()
[ 2.166320] L3 custom error: MASTER:MPU TARGET:L4 PER2
[ 2.166320] Modules linked in:
[ 2.166351] CPU: 0 PID: 0 Comm: swapper/0 Not
