On Thu, Apr 24, 2014 at 11:11 PM, Ezequiel Garcia
wrote:
> The DMA controller is needed for the USB controller to be correctly
> registered. Therefore, if the DMA node is located at the end an unecessary
> probe deferral is produced systematically.
>
> This is easily fixed by moving the node at th
On Tue, Apr 29, 2014 at 6:31 AM, George Cherian wrote:
> On 4/28/2014 9:47 PM, Yegor Yefremov wrote:
>>
>> On Mon, Apr 28, 2014 at 4:25 PM, George Cherian
>> wrote:
>>>
>>> On 4/28/2014 2:07 PM, yegorsli...@googlemail.com wrote:
From: Yegor Yefremov
This patch creates unique
On Thu, Apr 24, 2014 at 10:29:50AM +0300, Peter Ujfalusi wrote:
> It helps to identify issues if we have some information regarding to the
> channel which the event is associated.
>
> Signed-off-by: Peter Ujfalusi
> Acked-by: Joel Fernandes
Applied, thanks
--
~Vinod
--
To unsubscribe from thi
On 28/04/14 19:45, Tony Lindgren wrote:
> * Tomi Valkeinen [140427 23:53]:
>> On 25/04/14 18:31, Tony Lindgren wrote:
>>
>>> Chances are any mux register in the syscon area already works with
>>> pinctrl-single,pins or pinctrl-single,bits option. The ones in the
>>> padconf area should be already
On 4/28/2014 9:47 PM, Yegor Yefremov wrote:
On Mon, Apr 28, 2014 at 4:25 PM, George Cherian wrote:
On 4/28/2014 2:07 PM, yegorsli...@googlemail.com wrote:
From: Yegor Yefremov
This patch creates unique DMA channels for the second USB
interface, otherwise the second USB interface is not usabl
Hi Richard,
On 4/28/2014 9:48 PM, Richard Cochran wrote:
On Mon, Apr 28, 2014 at 06:25:56PM +0530, George Cherian wrote:
In beagle bone white (AM335x) CPTS has a choice of 2 clocksource
-dpll_core_m5_ck
-dpll_core_m4_ck
and by default dpll_core_m5_ck is used. Where as in AM437x the
default cl
On Mon, Apr 28, 2014 at 07:56:06PM +0200, Pavel Machek wrote:
> On Mon 2014-04-28 22:24:36, Jenny Tc wrote:
> > Dmitry/Pavel,
> >
> > Request your feedback on this. Fixed the comments from Pavel and waiting
> > for
> > your feedback on the changes
>
> IIRC, my latest comments were "this is comp
On Tue, Apr 29, 2014 at 09:02:27AM +0900, Simon Horman wrote:
> On Mon, Apr 28, 2014 at 08:30:32PM +0100, Russell King wrote:
> > Since we now automatically enable early BRESP in core L2C-310 code when
> > we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
> > explicitly. Instead,
On Mon, Apr 28, 2014 at 08:30:32PM +0100, Russell King wrote:
> Since we now automatically enable early BRESP in core L2C-310 code when
> we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
> explicitly. Instead, they should seek to preserve the value of bit 30
> in the auxiliary c
On Mon, Apr 28, 2014 at 07:58:43PM +, Paul Zimmerman wrote:
> > From: linux-usb-ow...@vger.kernel.org
> > [mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of Felipe Balbi
> > Sent: Monday, April 28, 2014 8:56 AM
> >
> > On Mon, Apr 28, 2014 at 04:49:23PM -0400, Zhuang Jin Can wrote:
> > > A
Hello Arnd,
Thanks a lot for the patch.
On 04/28/2014 11:07 AM, Arnd Bergmann wrote:
> Commit 4df42de9d3e "gpio: omap: add a GPIO_OMAP option instead of using
> ARCH_OMAP" made it possible to build OMAP kernels without the GPIO driver,
> which at least on OMAP2 and OMAP3 causes build errors becau
On Wed, 16 Apr 2014, Sourav Poddar wrote:
> These adds hwmod data for hdq/1w driver.
>
> Signed-off-by: Sourav Poddar
Is a TRM available yet for AM43x so this patch can be properly reviewed?
- Paul
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To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a messa
On Thu, 24 Apr 2014, Kevin Hilman wrote:
> Unfortunately, my OMAP1 (omap5912/OSK[1]) died last year and I haven't been
> able to get it booting again. I wonder if Spectrum Digital still has
> these available? Their websites[1] says "call for price."
>
> Kevin
>
> [1] http://www.spectrumdigital
On Mon, 21 Apr 2014, Laurent Pinchart wrote:
> From: Laurent Pinchart
>
> Commit 7b2e1277598e4187c9be3e61fd9b0f0423f97986 ("ARM: OMAP3: clock:
> Back-propagate rate change from cam_mclk to dpll4_m5") enabled clock
> rate back-propagation from cam_mclk do dpll4_m5 on OMAP3630 only.
> Perform back
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez
Cc: Enric Balletbo i Serra
---
arch/arm/boot/dts/am335x-igep0033.dtsi | 38 +-
1 file changed, 19 insertions(+), 19 del
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez
---
arch/arm/boot/dts/am335x-evmsk.dts | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez
---
arch/arm/boot/dts/am335x-evm.dts | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/a
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
Signed-off-by: Guido Martínez
---
arch/arm/boot/dts/am335x-bone-common.dtsi | 38 +++
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch
The granular residue accounting code uses certain variables specifically
for residue accounting. Document these in the structure declaration.
Also move around some elements and group them together.
Cc: Thomas Gleixner
Signed-off-by: Joel Fernandes
---
drivers/dma/edma.c | 26 +
edma param struct is now within an edma_pset struct introduced in Thomas
Gleixner's edma tx status series. Update memcpy function for the same.
Cc: Thomas Gleixner
Signed-off-by: Joel Fernandes
---
drivers/dma/edma.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dri
On 04/28/2014 05:49 AM, Thomas Gleixner wrote:
> A simpler version to provide granular residue accounting and readout
> for EDMA.
>
> Delta to V1:
>
> - Removed the double read of the address in PaRAM
>
> - Simplified the stats update in the interrupt callback for
> intermedi
Hello.
On 04/28/2014 06:01 PM, Roger Quadros wrote:
Add "wkupclk" and "refclk" information to DT binding information.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bi
On 04/28/2014 01:30 PM, Russell King wrote:
> We have a mixture of different devices with different register layouts,
> but we group all the bits together in an opaque mess. Split them out
> into those which are L2C-310 specific and ones which refer to earlier
> devices. Provide full auxiliary co
On 04/28/2014 01:30 PM, Russell King wrote:
> Since we now automatically enable early BRESP in core L2C-310 code when
> we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
> explicitly. Instead, they should seek to preserve the value of bit 30
> in the auxiliary control register.
> From: linux-usb-ow...@vger.kernel.org
> [mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of Felipe Balbi
> Sent: Monday, April 28, 2014 8:56 AM
>
> On Mon, Apr 28, 2014 at 04:49:23PM -0400, Zhuang Jin Can wrote:
> > Adds a debugfs file "snapshot" to dump dwc3 requests, trbs and events.
< sni
On 04/28/2014 03:17 PM, Stefan Roese wrote:
> From: Jarkko Nikula
>
Same authorship and commit log notes here than to 2/5. One important
note below.
> --- /dev/null
> +++ b/sound/soc/omap/ha-dsp-card.c
> @@ -0,0 +1,307 @@
> +/*
> + * ha-dsp-card.c -- SoC audio HA-DSP add-on card for TAO-3530
>
Hi Stefan
On 04/28/2014 03:17 PM, Stefan Roese wrote:
> From: Jarkko Nikula
>
> This codec driver template represents an I2C controlled multichannel audio
> codec that has many typical ASoC codec driver features like volume controls,
> mixer stages, mux selection, output power control, in-codec
On 04/28/2014 03:17 PM, Stefan Roese wrote:
> From: Jarkko Nikula
>
Same authorship and commit log notes here than to 2/5. One important
comment below.
> --- /dev/null
> +++ b/sound/soc/omap/ha-dsp-card.c
> @@ -0,0 +1,307 @@
> +/*
> + * ha-dsp-card.c -- SoC audio HA-DSP add-on card for TAO-353
Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set. Set it in
core code and remove it from OMAP4. Remove the NS access bit for the
interrupt registers from OMAP4 as well - nothing in the kernel accesses
that yet, and we c
From: Sekhar Nori
To: linux-arm-ker...@lists.ifradead.org
L2 cache initialization for OMAP4 redundantly sets the cache policy to
Round-Robin. This is not needed since thats the PL310 default anyway.
Removing this reduces the number of platform specific aux control
settings.
Signed-off-by: Sekha
From: Sekhar Nori
To: linux-arm-ker...@lists.ifradead.org
Add support for L2 cache controller (PL310) on AM437x SoC.
Signed-off-by: Sekhar Nori
Acked-by: Santosh Shilimkar
Signed-off-by: Russell King
---
arch/arm/mach-omap2/Kconfig | 1 +
arch/arm/mach-omap2/io.c| 1 +
2 files changed, 2
From: Sekhar Nori
To: linux-arm-ker...@lists.ifradead.org
Get rid of init call to initialize L2 cache. Instead use the init_early
machine hook. This helps in using the initialization routine across
SoCs without the need of ugly cpu_is_*() checks.
Signed-off-by: Sekhar Nori
Acked-by: Santosh Sh
Avoid reading directly from the L2 registers in platform code. The L2
code will have already saved the register values itself into the
l2x0_saved_regs structure, so platform code should just move these
values to where they're required.
This is safe because the L2x0 will have been initialised by a
Acked-by: Tony Lindgren
Signed-off-by: Russell King
---
arch/arm/mach-omap2/omap4-common.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index 9ce52548a484..06c6a181d6ad 100644
--- a/arch/arm/m
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.
Acked-by: Tony Lindgren
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren
Signed-off-by: Russell King
Now that OMAP2 uses the write_sec method, we don't need to enable the L2
cache in OMAP2 specific code; this can be done via the normal mechanisms
in the L2C code. Remove the OMAP2 specific code.
Acked-by: Tony Lindgren
Signed-off-by: Russell King
---
arch/arm/mach-omap2/omap4-common.c | 5
With the write_sec method, we no longer need to override the default
L2C disable method, and we no longer need the L2C set_debug method.
Both of these can be handled via the write_sec method.
Acked-by: Tony Lindgren
Signed-off-by: Russell King
---
arch/arm/mach-omap2/omap4-common.c | 42 +++
On Wed, 16 Apr 2014, Sourav Poddar wrote:
> For SOCs with dt enabled, device should be build through device tree.
> Prevent device build call from platform code, if device tree is
> enabled.
>
> Signed-off-by: Sourav Poddar
Isn't OMAP2+ only supporting DT device enumeration now?
- Paul
--
To
Santosh says:
> But we should kill all of that since we long back decided to remove
> ES1.0 related code. The mach-omap code alreasy has removed the ES1.0
> compatibility so feel free to remove any specific ES1.0
> related stuff. That silicon is long dead.
Acked-by: Tony Lindgren
Signed-off-by: R
On Wed, 16 Apr 2014, Sourav Poddar wrote:
> The patch adds the following to the omap hdq driver.
> 1. HDQ Device reset call in probe.
> 2. Enabling '1 wire mode' and checking for presence pulse bit.
> 3. Proper disabling and enabling of interrupts during read path.
> 4. Add re-initialization code
On 04/28/2014 12:20 PM, Joel Fernandes wrote:
> On 04/28/2014 11:43 AM, Dave Martin wrote:
>> On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
>>> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
>>> (Cortex A15) fails to come up causing SMP boot on second
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On Mon 2014-04-28 22:24:36, Jenny Tc wrote:
> Dmitry/Pavel,
>
> Request your feedback on this. Fixed the comments from Pavel and waiting for
> your feedback on the changes
IIRC, my latest comments were "this is completely misdesigned, it is
using strings and table searches where it should use po
On Mon, Apr 28, 2014 at 06:28:45PM +, Paul Walmsley wrote:
> On Wed, 16 Apr 2014, Sourav Poddar wrote:
>
> > For SOCs with dt enabled, device should be build through device tree.
> > Prevent device build call from platform code, if device tree is
> > enabled.
> >
> > Signed-off-by: Sourav Pod
On 04/28/2014 11:43 AM, Dave Martin wrote:
> On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
>> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
>> (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
>> seems to be because the CP
* Tomi Valkeinen [140427 23:53]:
> On 25/04/14 18:31, Tony Lindgren wrote:
>
> > Chances are any mux register in the syscon area already works with
> > pinctrl-single,pins or pinctrl-single,bits option. The ones in the
> > padconf area should be already mapped so the driver just has to
> > reques
On Tue, Apr 22, 2014 at 01:31:46PM -0500, Joel Fernandes wrote:
> On my DRA7 system, when the kernel is built in THUMB mode, the secondary CPU
> (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
> seems to be because the CPU is in ARM mode once the ROM hands over control
=
> [ INFO: possible recursive locking detected ]
> 3.15.0-rc2-next-20140428-2-gd0ca5e6 #1 Not tainted
> -
> swapper/0/0 is trying to acquire lock:
> (console_lock){+.+...}, at: [] con_init+0x
On 04/26/2014 11:36 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 26-04-2014 3:02, Joel Fernandes wrote:
>
>> DRA7xx SoCs have a DES3DES IP. Add DT data for the same.
>
>> Signed-off-by: Joel Fernandes
>> ---
>> arch/arm/boot/dts/dra7.dtsi | 11 +++
>> 1 file changed, 11 insertions(+)
On Mon, Apr 28, 2014 at 06:25:56PM +0530, George Cherian wrote:
> In beagle bone white (AM335x) CPTS has a choice of 2 clocksource
> -dpll_core_m5_ck
> -dpll_core_m4_ck
> and by default dpll_core_m5_ck is used. Where as in AM437x the
> default clocksource used is dpll_core_m4_ck .
Is your patch
On Mon, Apr 28, 2014 at 4:25 PM, George Cherian wrote:
> On 4/28/2014 2:07 PM, yegorsli...@googlemail.com wrote:
>>
>> From: Yegor Yefremov
>>
>> This patch creates unique DMA channels for the second USB
>> interface, otherwise the second USB interface is not usable
>> at all.
>
> MUSB_DMA_NUM_CH
* Tomi Valkeinen [140428 03:44]:
> On 26/04/14 02:53, Tony Lindgren wrote:
> > * Tomi Valkeinen [140424 02:53]:
> >> On 18/04/14 18:51, Tony Lindgren wrote:
> >>
> +gpio = of_get_gpio(node, 0);
> +if (gpio_is_valid(gpio) || gpio == -ENOENT) {
> +ddat
On Mon, Apr 28, 2014 at 08:11:33PM +0530, George Cherian wrote:
> On 4/28/2014 7:28 PM, Guido Martínez wrote:
> >Use phandles instead of unit adresses to reference usb and dma nodes.
> >This makes the DT more robust and readable.
> The series will give dtb build errors
> Error: arch/arm/boot/dts/am
* Lee Jones [140428 04:37]:
> > The twl4030 PMIC needs to be configured properly for things like
> > warm reset and deeper idle states so the PMIC manages the regulators
> > properly based on the hardware triggers from the SoC.
> >
> > For example, when rebooting an OMAP3530 at 125 MHz, it hangs.
On Mon, Apr 28, 2014 at 05:01:27PM +0300, Roger Quadros wrote:
> Add USB pinmux information and USB modes
> for the USB controllers.
>
> Signed-off-by: Roger Quadros
Reviewed-by: Felipe Balbi
> ---
> arch/arm/boot/dts/dra7-evm.dts | 24
> 1 file changed, 24 insertions
On Mon, Apr 28, 2014 at 05:01:26PM +0300, Roger Quadros wrote:
> Add nodes for the Super Speed USB controllers, omap-control-usb,
> USB2 PHY and USB3 PHY devices.
>
> Remove ocp2scp1 address space from hwmod data as it is
> now provided via device tree.
>
> Signed-off-by: Roger Quadros
Reviewed
On Mon, Apr 28, 2014 at 05:01:25PM +0300, Roger Quadros wrote:
> Add "wkupclk" and "refclk" information to DT binding information.
>
> Signed-off-by: Roger Quadros
Reviewed-by: Felipe Balbi
> ---
> Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++
> 1 file changed, 7 insertions(+)
On Mon, Apr 28, 2014 at 05:01:24PM +0300, Roger Quadros wrote:
> The USB2 PHY driver expects named clocks for wakeup clock
> and reference clock. Provide this information for USB2 PHY
> nodes in OMAP4 and OMAP5 SoC DTS.
>
> Signed-off-by: Roger Quadros
Reviewed-by: Felipe Balbi
> ---
> arch/a
Hi,
On Mon, Apr 28, 2014 at 05:01:23PM +0300, Roger Quadros wrote:
> As clocks might be named differently on multiple platforms, use a generic
> name in the driver and allow device tree node to specify the platform
> specific clock name.
>
> Signed-off-by: Roger Quadros
> ---
> drivers/phy/phy-
On Mon, Apr 28, 2014 at 04:49:23PM -0400, Zhuang Jin Can wrote:
> Adds a debugfs file "snapshot" to dump dwc3 requests, trbs and events.
you need to explain what are you trying to provide to our users here.
What "problem" are you trying to solve ?
> As ep0 requests are more complex than others.
Today we get error such as
L3 Custom Error: MASTER MPU TARGET L4PER2
But since the actual instruction triggerring the error Vs the point
at which we report error may not be aligned, it makes sense to try
and provide additional information - example the type of operation
that was attempted to being
As per Documentation (OMAP4+), then masterid is infact encoded as
follows:
"L3_TARG_STDERRLOG_MSTADDR[7:0] STDERRLOG_MSTADDR stores the NTTP
master address. The master address is the concatenation of Prefix &
Initiator ConnID. It is defined on 8 bits. The 6 MSBs are used to
distinguish the differen
On Mon, 28 Apr 2014, Tony Lindgren wrote:
> * Lee Jones [140428 04:42]:
> > > These settings are based on the "Recommended Sleep Sequences for
> > > the Zoom Platform" pdf at:
> > >
> > > http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
> > >
> > > These settings assume most
From: Sricharan R
Since omap_l3_noc driver is now being used for OMAP5 and reusable with
DRA7 and AM437x, using omap4 specific naming is misleading.
Signed-off-by: Sricharan R
Signed-off-by: Nishanth Menon
Acked-by: Santosh Shilimkar
Acked-by: Peter Ujfalusi
Tested-by: Darren Etheridge
---
From: Rajendra Nayak
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
<0x4400 0x100> is clk1 and clk2 is the sub clock domain
<0x4500 0x1000> is clk3
Add all the data needed
Move the L3 master structure out of the static definition to enable
reuse for other SoCs.
Signed-off-by: Nishanth Menon
Acked-by: Santosh Shilimkar
Acked-by: Peter Ujfalusi
Tested-by: Darren Etheridge
---
V3: no change
drivers/bus/omap_l3_noc.h | 15 +++
1 file changed, 11 inser
Currently the target instance information is organized indexed by bit
field offset into multiple arrays.
1. We currently have offsets specific to each target associated with each
clock domains are in seperate arrays:
l3_targ_inst_clk1
l3_targ_inst_clk2
l3_targ_inst_clk3
2. Then they are organize
From: Rajendra Nayak
On DRA7, unlike on OMAP4 and OMAP5, the flag mux input numbers used
to indicate the source of errors are not continous. Have a way in the
driver to catch these and WARN the user of the flag mux input thats
either undocumented or wrong.
In the similar vein, Timeout errors in
From: Afzal Mohammed
Add AM4372 information to handle L3 error.
AM4372 has two clk domains 100f and 200s. Provide flagmux and data
associated with it.
NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware
team, L3 timeout error cannot be cleared the normal way (by setting
bit 31
This allows us to encompass target information and flag mux offset that
points to the target information into a singular structure. This saves
us the need to look up two different arrays indexed by module ID for
information.
This allows us to reduce the static target information allocation to
just
* Lee Jones [140428 04:47]:
> > With the recommended twl4030 configuration added, we can now add
> > board specific changes as modifications to the recommended
> > configuration.
> >
> > Cc: Peter De Schrijver
> > Cc: Samuel Ortiz
> > Cc: Lee Jones
> > Signed-off-by: Tony Lindgren
> > ---
> >
This is an embarrassing patch :(.
Texas Corporation does not make OMAP. Texas Instruments Inc does.
For that matter I dont seem to be able to find a Texas Corporation on
the internet either.
While at it, update coverage to the current year and update the template
to remove redundant information
just simplify derefencing that is equivalent.
Signed-off-by: Nishanth Menon
Acked-by: Santosh Shilimkar
Acked-by: Peter Ujfalusi
Tested-by: Darren Etheridge
---
V3: no change
drivers/bus/omap_l3_noc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bus/omap_l3_n
The following V3 of the series is based on v3.15-rc1 + peter's patch series:
patch #1: https://patchwork.kernel.org/patch/3923141/
(drivers: bus: omap_l3: Convert to use devm_kzalloc)
patch #2: https://patchwork.kernel.org/patch/3923061/
(drivers: bus: omap_l3: Conv
From: Sricharan R
DRA7xx SoC has the same l3-noc interconnect ip (as OMAP4 and OMAP5), but
AM437x SoC has just 2 modules instead of 3 which other SoCs have.
So, stop using direct access of array indices and use of->match data and
simplify implementation to benefit future usage.
While at it, ren
* Lee Jones [140428 04:42]:
> > These settings are based on the "Recommended Sleep Sequences for
> > the Zoom Platform" pdf at:
> >
> > http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
> >
> > These settings assume most of the regulators are under control of
> > Linux, and cut
we do not use iclk directly anymore. And, even if we had to, we
should be using pm_runtime APIs to do the same to be completely SoC
independent.
Signed-off-by: Nishanth Menon
Acked-by: Santosh Shilimkar
Acked-by: Peter Ujfalusi
Tested-by: Darren Etheridge
---
change in V3: none
drivers/bus/om
From: Afzal Mohammed
Errors that cannot be cleared (determined by reading REGERR register)
are currently handled by masking it. Documentation states that REGERR
"Checks which application/debug error sources are active" - it does not
indicate that this is "interrupt status" - masked out status rep
The logic between handling CUSTOM_ERROR and STANDARD_ERROR is just the
reporting style.
So make it generic, simplify and standardize the reporting with both
master and target information printed to log.
Handle the register address difference for master code for standard
error and custom error as
Current interrupt handler does the first level parse to identify the
slave and then handles the slave even identification, reporting and
clearing of event as well. It is hence logical to split the handler
into two where the primary handler just parses the flagmux till it
identifies a slave and the
L3 error may be triggered using Debug interface (example JTAG) or
due to other errors, for example an opcode fetch (due to function
pointer or stack corruption) or a data access (due to some other
failure). NOC registers contain additional information to help aid
debug information.
With this, we c
Currently we use __raw_readl and writel in this driver. Considering
there is no specific need for a memory barrier, replacing writel
with endian-neutral writel_relaxed and replacing __raw_readls with
the corresponding endian-neutral readl_relaxed allows us to have a
standard set of register operati
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.
To better represent this in the driver, we use the concept of submodule.
The address defintions in the devicetree is as per the high level
clock domain(module
l3->dev is not populated, so populate it and use it to print information
relevant to the device instead of using a generic pr_*.
Signed-off-by: Nishanth Menon
Acked-by: Santosh Shilimkar
Acked-by: Peter Ujfalusi
Tested-by: Darren Etheridge
---
change in V3: none
drivers/bus/omap_l3_noc.c |
On 04/28/2014 02:17 PM, Stefan Roese wrote:
From: Jarkko Nikula
This codec driver template represents an I2C controlled multichannel audio
codec that has many typical ASoC codec driver features like volume controls,
mixer stages, mux selection, output power control, in-codec audio routings,
cod
On 4/28/2014 8:01 PM, Felipe Balbi wrote:
On Mon, Apr 28, 2014 at 09:40:20AM +0530, George Cherian wrote:
CPTS refclk name is hardcoded, which makes it fail in case of DRA7x
Remove the hardcoded clock name for CPTS refclk and get the same from DT.
Signed-off-by: George Cherian
---
drivers/ne
On 4/28/2014 7:28 PM, Guido Martínez wrote:
Use phandles instead of unit adresses to reference usb and dma nodes.
This makes the DT more robust and readable.
The series will give dtb build errors
Error: arch/arm/boot/dts/am335x-bone-common.dtsi:186.2-15 syntax error
FATAL ERROR: Unable to parse
On Mon, Apr 28, 2014 at 09:40:20AM +0530, George Cherian wrote:
> CPTS refclk name is hardcoded, which makes it fail in case of DRA7x
> Remove the hardcoded clock name for CPTS refclk and get the same from DT.
>
> Signed-off-by: George Cherian
> ---
> drivers/net/ethernet/ti/cpts.c | 11
On 4/28/2014 2:07 PM, yegorsli...@googlemail.com wrote:
From: Yegor Yefremov
This patch creates unique DMA channels for the second USB
interface, otherwise the second USB interface is not usable
at all.
MUSB_DMA_NUM_CHANNELS is 15, so if you pass any dma-names > 15 (>
rx15/tx15),
the dma_cont
Mark the array and the string const by using "static const char * const
foo[]" instead of "static const char* foo[]".
Signed-off-by: Sebastian Reichel
---
sound/soc/omap/rx51.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51
On Sun, Apr 06, 2014 at 01:52:03PM +0200, Sebastian Reichel wrote:
> This is an RFC patch adding DT support to the si4713 radio
> transmitter i2c driver.
ping?
-- Sebastian
signature.asc
Description: Digital signature
This patch adds support for specifying auxiliary codecs and
codec configuration via device tree phandles.
This change adds new fields to snd_soc_aux_dev and snd_soc_codec_conf
and adds support for the changes to SoC core methods.
Signed-off-by: Pavel Machek
Signed-off-by: Sebastian Reichel
---
This patch converts the rx51 ASoC module to use
devm_snd_soc_register_card.
Signed-off-by: Pali Rohár
Signed-off-by: Sebastian Reichel
---
sound/soc/omap/rx51.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/sound/soc/omap/rx51.c
Add module alias to support driver autoloading.
Signed-off-by: Pali Rohár
Signed-off-by: Sebastian Reichel
---
sound/soc/omap/rx51.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c
index 1a3f05c..55713d0 100644
--- a/sound/soc/omap/rx51.c
+++ b/
This is a preparation for DT based booting where the McBSP id
is set to -1 for all McBSP instances.
Signed-off-by: Sebastian Reichel
---
sound/soc/omap/omap-mcbsp.c | 5 +++--
sound/soc/omap/omap-mcbsp.h | 2 +-
sound/soc/omap/rx51.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
Update the driver to get GPIO numbers from the
devm gpiod API instead of requesting hardcoded
GPIO numbers.
Signed-off-by: Sebastian Reichel
---
sound/soc/omap/rx51.c | 114 ++
1 file changed, 79 insertions(+), 35 deletions(-)
diff --git a/sound/s
Add more error messages making it easier to identify problems.
Signed-off-by: Sebastian Reichel
---
sound/soc/omap/rx51.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c
index 30cfac0..110deca 100644
--- a/sound/
Ping ?
On Monday 21 April 2014 15:06:23 Laurent Pinchart wrote:
> From: Laurent Pinchart
>
> Commit 7b2e1277598e4187c9be3e61fd9b0f0423f97986 ("ARM: OMAP3: clock:
> Back-propagate rate change from cam_mclk to dpll4_m5") enabled clock
> rate back-propagation from cam_mclk do dpll4_m5 on OMAP3630 o
This patch adds device tree support to the Nokia N900 audio driver and
adds documentation for the DT binding.
Signed-off-by: Sebastian Reichel
---
.../devicetree/bindings/sound/nokia,rx51.txt | 27 +++
sound/soc/omap/rx51.c | 53 ++
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